Pll Signals; Intel ® Flexible Display Interface Signals; Intel ® Flexible Display Interface - Intel BX80605X3430 - Xeon 2.4 GHz Processor Datasheet

Data sheet
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6.6

PLL Signals

Table 6-8.

PLL Signals

Signal Name
BCLK[0]
BCLK#[0]
BCLK[1]
BCLK#[1]
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
®
6.7
Intel
Note:
The signals noted below as not being used are included for reference to define all LGA
1156 land locations. These signals will be used by future processors that are
compatible with LGA 1156 platforms.
®
Table 6-9.
Intel
Flexible Display Interface
Signal Name
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]
FDI_TX[3:0]
FDI_TX#[3:0]
FDI_TX[7:4]
FDI_TX#[7:4]
54
Differential bus clock input to the processor.
Differential bus clock input to the processor. Reserved
for possible future use.
Buffered differential bus clock pair to ITP..
Differential PCI Express / DMI Clock In:
These pins receive a 100-MHz Serial Reference clock.
This clock is used to generate the clocks necessary for
the support of PCI Express. This also is the reference
®
clock for Intel
Flexible Display Interface.
Flexible Display Interface Signals
®
Intel
Flexible Display Interface Frame Sync—Pipe A.
Note: This signal is not used by the processor. It is
connected to V
on the package.
SS
®
Intel
Flexible Display Interface Frame Sync—Pipe B.
Note: This signal is not used by the processor. It is
connected to V
on the package.
SS
®
Intel
Flexible Display Interface Hot Plug Interrupt.
Note: This signal is not used by the processor. It is
connected to V
on the package.
SS
®
Intel
Flexible Display Interface Line Sync—Pipe A.
Note: This signal is not used by the processor. It is
connected to V
on the package.
SS
®
Intel
Flexible Display Interface Line Sync—Pipe B.
Note: This signal is not used by the processor. It is
connected to V
on the package.
SS
®
Intel
Flexible Display Interface Transmit Differential
Pair—Pipe A..
Note: These signals are not used by the processor.
They are connected to V
®
Intel
Flexible Display Interface Transmit Differential
Pair—Pipe B.
Note: These signals are not used by the processor.
They are connected to V
Description
Description
on the package.
SS
on the package.
SS
Signal Description
Direction
Type
I
Diff Clk
I
Diff Clk
O
Diff Clk
I
Diff Clk
Direction
Type
Datasheet, Volume 1

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