Dmi; Pll Signals; Table 6-27 Dmi - Processor To Pch Serial Interface; Table 6-28 Pll Signals - Intel P4000 - DATASHEET REV 001 Datasheet

Signal Description
Table 6-26.Intel® Flexible Display Interface (Sheet 2 of 2)
Signal Name
FDI_TX[7:4]
FDI_TX#[7:4]
FDI_FSYNC[1]
FDI_LSYNC[1]
6.7

DMI

Table 6-27.DMI - Processor to PCH Serial Interface
Signal Name
DMI_RX[3:0]
DMI_RX#[3:0]
DMI_TX[3:0]
DMI_TX#[3:0]
6.8

PLL Signals

Table 6-28.PLL Signals
Signal Name
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
Datasheet
Intel® Flexible Display Interface
Transmit Differential Pair - Pipe B
Intel® Flexible Display Interface Frame
Sync - Pipe B
Intel® Flexible Display Interface Line Sync
- Pipe B
FDI_INT Intel® Flexible Display Interface Hot Plug
Interrupt
DMI Input from PCH: Direct Media
Interface receive differential pair.
DMI Output to PCH: Direct Media
Interface transmit differential pair.
BCLK Differential bus clock input to the processor
BCLK#
Buffered differential bus clock pair to ITP
Differential PCI Express Based
Graphics/DMI Clock In: These pins receive
a 100-MHz Serial Reference clock from the
external clock synthesizer. This clock is used
to generate the clocks necessary for the
support of PCI Express. This also is the
reference clock for Intel® FDI.
Embedded Display Port PLL Differential
Clock In: With or without SSC -120 MHz.
Description
Description
Description
Direction/Buffer
Type
O
FDI
I
CMOS
I
CMOS
I
CMOS
Direction/Buffer
Type
I
DMI
O
DMI
Direction/Buffer
Type
I
Diff Clk
O
Diff Clk
I
Diff Clk
I
Diff Clk
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