Il(02) And Ilc(03) - Omron CQM1H - PROGRAM Programming Manual

INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)
DIFU(13) and DIFD(14) in
Interlocks
00000
00001
ON
00000
OFF
ON
00001
OFF
ON
01000
OFF
Precautions
Flags
228
If the execution condition for IL(02) is OFF, the interlocked section between
IL(02) and ILC(03) will be treated as shown in the following table:
Instruction
OUT and OUT NOT
TIM and TIMH(15)
CNT, CNTR(12)
KEEP(11)
DIFU(13) and
DIFD(14)
All other instructions
IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be
used several times in a row, with each IL(02) creating an interlocked section
through the next ILC(03). ILC(03) cannot be used unless there is at least one
IL(02) between it and any previous ILC(03).
Changes in the execution condition for a DIFU(13) or DIFD(14) are not
recorded if the DIFU(13) or DIFD(14) is in an interlocked section and the exe-
cution condition for the IL(02) is OFF. When DIFU(13) or DIFD(14) is execu-
tion in an interlocked section immediately after the execution condition for the
IL(02) has gone ON, the execution condition for the DIFU(13) or DIFD(14) will
be compared to the execution condition that existed before the interlock
became effective (i.e., before the interlock condition for IL(02) went OFF). The
ladder diagram and bit status changes for this are shown below. The interlock
is in effect while 00000 is OFF. Notice that 01000 is not turned ON at the point
labeled A even though 00001 has turned OFF and then back ON.
DIFU(13) 01000
A
There must be an ILC(03) following any one or more IL(02).
Although as many IL(02) instructions as are necessary can be used with one
ILC(03), ILC(03) instructions cannot be used consecutively without at least
one IL(02) in between, i.e., nesting is not possible. Whenever a ILC(03) is exe-
cuted, all interlocks between the active ILC(03) and the preceding ILC(03) are
cleared.
When more than one IL(02) is used with a single ILC(03), an error message
will appear when the program check is performed, but execution will proceed
normally.
There are no flags affected by these instructions.
Treatment
Designated bit turned OFF.
Reset.
PV maintained.
Bit status maintained.
Not executed (see below).
The instructions are not executed, and all IR, AR, LR, HR,
and SR bits and words written to as operands in the
instructions are turned OFF.
Address Instruction
IL(02)
00000 LD
00001 IL(02)
00002 LD
ILC(03)
00003 DIFU(13)
00004 ILC(03)
Section 5-12
Operands
00000
00001
01000