Omron CQM1H - PROGRAM Programming Manual

Programmable controllers; inner boards

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Cat. No. W364-E1-05

SYSMAC CQM1H Series

CQM1H-CPU@@ Programmable Controllers

CQM1H-@@@@@ Inner Boards

PROGRAMMING MANUAL

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Troubleshooting

Summary of Contents for Omron CQM1H - PROGRAM

Page 1 Cat. No. W364-E1-05 SYSMAC CQM1H Series CQM1H-CPU@@ Programmable Controllers CQM1H-@@@@@ Inner Boards PROGRAMMING MANUAL...
Page 2 SYSMAC CQM1H Series CQM1H-CPU@@ Programmable Controllers CQM1H-@@@@@ Inner Boards Programming Manual Revised September 2007...
Page 4  OMRON, 1999 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form, or by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permission of OMRON.
Page 6: Table Of Contents
Basic PC Operation and I/O Processes ........
Page 7 Instruction Format ..........Data Areas, Definer Values, and Flags ....... . .
Page 8 Error and Arithmetic Flag Operation ........
Page 10: About This Manual
Board. Only an outline of this Board is provided in Section 2. Section 3 describes the structure of the PC’s memory areas, and explains how to use them. It also describes Memory Cassette operations used to transfer data between the CPU Unit and a Memory Cassette.
Page 12 WHETHER SUCH CLAIM IS BASED ON CONTRACT, WARRANTY, NEGLIGENCE, OR STRICT LIABILITY. In no event shall the responsibility of OMRON for any act exceed the individual price of the product on which liability is asserted. IN NO EVENT SHALL OMRON BE RESPONSIBLE FOR WARRANTY, REPAIR, OR OTHER CLAIMS...
Page 13 The following are some examples of applications for which particular attention must be given. This is not intended to be an exhaustive list of all possible uses of the products, nor is it intended to imply that the uses listed may be suitable for the products: •...
Page 14 PERFORMANCE DATA Performance data given in this manual is provided as a guide for the user in determining suitability and does not constitute a warranty. It may represent the result of OMRON's test conditions, and the users must correlate it to actual application requirements.
Page 16: Format
Conformance to EC Directives ........
Page 17: Intended Audience
!WARNING It is extremely important that a PC and all PC Units be used for the specified purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PC System to the above-mentioned applica- tions.
Page 18 I/O memory area. Doing either of these without confirming safety may result in injury. !Caution Tighten the screws on the terminal block of the AC Power Supply Unit to the torque specified in the operation manual. The loose screws may result in...
Page 19: Operating Environment Precautions
• Locations subject to possible exposure to radioactivity. • Locations close to power supplies. !Caution The operating environment of the PC System can have a large effect on the longevity and reliability of the system. Improper operating environments can lead to malfunction, failure, and other unforeseeable problems with the PC System.
Page 20 BUSY indicator to go out before removing the Memory Card. • If the I/O Hold Bit (SR 25212) is turned ON, the outputs from the PC will not be turned OFF and will maintain their previous status when the PC is switched from RUN or MONITOR mode to PROGRAM mode.
Page 21 The product will be destroyed if 200 to 240 V AC is supplied while the metal jumper is attached. • A ground of 100 Ω or less must be installed when shorting the GR and LG terminals on the Power Supply Unit.
Page 22 • UL standards required that batteries be replaced only by experienced technicians. Do not allow unqualified persons to replace batteries. • When replacing parts, be sure to confirm that the rating of a new part is correct. Not doing so may result in malfunction or burning.
Page 23: Conformance To Ec Directives
EN61000-6-4 (Radiated emission: 10-m regulations) Low Voltage Directive Always ensure that devices operating at voltages of 50 to 1,000 V AC or 75 to 1,500 V DC meet the required safety standards for the PC (EN61131-2). Conformance to EC Directives The CQM1H-series PCs comply with EC Directives.
Page 24 PC. Countermeasures taken to satisfy the standards vary depending on the devices on the load side, wiring, configuration of machines, etc. Following are examples of countermeasures for reducing the generated noise. Countermeasures Refer to EN61000-6-4 for more details.
Page 25: Conformance To Ec Directives
Conformance to EC Directives When switching a load with a high inrush current such as an incandescent lamp, suppress the inrush current as shown below. Countermeasure 1 Countermeasure 2 Providing a dark current of approx. Providing a limiting resistor one-third of the rated value through...
Page 26: Pc Setup And Other Features
High-speed Timers ........
Page 27: Pc Setup
The default values for the PC Setup are 0000 for all words. The default values for DM 6600 to DM 6655 can be reset at any time by turning ON SR 25210. !Caution When data memory (DM) is cleared from a Programming Device, the PC Setup settings will also be cleared to all zeros.
Page 28: Serial Communications Board Settings
Turns ON when there is an error in DM 6645 to DM 6655 (read regularly when power is ON). AR 0400 to AR 0407 An error code of 10 is written to this byte when there is an error in DM 6550 to DM 6559 (read reg- ularly when power is ON).
Page 29: Pc Setup Settings
Function Page Startup Processing (DM 6600 to DM 6614) The following settings are effective after transfer to the PC only after the PC is restarted. DM 6600 00 to 07 Startup Mode (effective when bits 08 to 15 are set to 02).
Page 30 00 to 03 Input Time Constant for IR 00000 to IR 00007 0: 8 ms; 1: 1 ms; 2: 2 ms; 3: 4 ms; 4: 8 ms; 5: 16 ms; 6: 32 ms; 7: 64 ms; 8: 128 ms 04 to 07...
Page 31 00: 4 digits; 01: 8 digits High-speed Counter Settings (DM 6640 to DM 6644) The following settings are effective after transfer to the PC the next time operation is started. Inner Board Slot 1 Settings (See 1-2 Inner Board Settings for details.)
Page 32 0: Disable; 1: Set 08 to 11 Link Words for 1:1 Data Link (1:1 data link master mode) 0: LR 00 to LR 63; 1: LR 00 to LR 31; 2: LR 00 to LR 15 12 to 15 Communications Mode 0: Host Link;...
Page 33 DM 6652 00 to 15 Transmission Delay (No-protocol or Slave-initiated Host Link communications only) 0000 to 9999 (BCD): Set in units of 10 ms, e.g., a setting of 0001 equals 10 ms DM 6653 00 to 07 Node Number (Host Link): 00 to 31 (BCD)
Page 34: Inner Board Settings
1-2-1 Settings for a Serial Communications Board Use the settings in DM 6613 and DM 6614 to set the servicing times for a Serial Communications Board mounted in Inner Board slot 1. (A Serial Com- munications Board cannot be mounted in slot 2.)
Page 35: Settings For A High-Speed Counter Board
1-2-2 Settings for a High-speed Counter Board The settings in DM 6602, DM 6640, and DM 6641 determine the operation of a High-speed Counter Board mounted in Inner Board slot 1. The settings in DM 6611, DM 6643, and DM 6644 determine the operation of a High-speed Counter Board mounted in Inner Board slot 2.
Page 36: Settings For A Pulse I/O Board
Settings for a Pulse I/O Board The settings in DM 6611, DM 6643, and DM 6644 determine the operation of a Pulse I/O Board mounted in Inner Board slot 2. (A Pulse I/O Board cannot be mounted in slot 1.)
Page 37: Basic Pc Operation And I/O Processes
This section explains the PC Setup settings related to basic operation and I/O processes. 1-3-1 Startup Mode The operating mode the PC will start in when power is turned ON can be set as shown below. DM 6600 Startup Mode Designation 00: Depends upon Programming Device and DIP switch settings (See table below.)
Page 38: Hold Bit Status
Make the settings shown below to determine whether, when the power supply is turned ON, the Forced Status Hold Bit (SR 25211) and/or I/O Hold Bit (SR 25212) will retain the status that was in effect when the power was last turned OFF, or whether the previous status will be cleared.
Page 39: Peripheral Port Servicing Time
Servicing time (%, valid when bits 08 to 15 are set to 01) 00 to 99 (BCD, two digits) Default: 5% of cycle time Example: If DM 6617 is set to 0115, the peripheral port will be serviced for 15% of the cycle time. The minimum servicing time is 0.256 ms.
Page 40: High-Speed Timers
DM 6627: IR 014 and IR 015 Time constant for IR 003, IR 005, IR 007, IR 009, IR 011, IR 013, and IR 015 Time constant for IR 002, IR 004, IR 006, IR 008, IR 010, IR 012, and IR 014 Default: 0000 (8 ms for each) The nine possible settings for the input time constant are shown below.
Page 41: Dsw(87) Input Digits And Output Refresh Method
1-3-9 Peripheral Port Settings Serial communications settings for the peripheral port are determined by pins 5 and 7 of the CPU Unit’s DIP switch, the hexadecimal setting in DM 6650, and the device connected to the peripheral port. DIP switch...
Page 42: Error Log Settings
AR area. Example If 0230 is set in DM 6618, an FALS 9F error will not occur until the cycle time exceeds 3 s. If the actual cycle time is 2.59 s, the current cycle time stored in the AR area will be 2590 (ms), but the cycle time read from a Programming Device will be 999.9 ms.
Page 43: Interrupt Functions
Make the settings shown below to determine whether or not a non-fatal error Log Operation (DM 6655) is to be generated when the cycle time exceeds 100 ms or when the voltage of the built-in battery drops, and to set the method for storing records in the error log when errors occur.
Page 44 High-speed Counter Board. A High-speed Counter Board can count pulses up to 50 kHz or 500 kHz. The high-speed counter PVs can be checked against a target value or an SV range and a bit pattern can be output inter- nally or externally instead of generating an interrupt.
Page 45 Section 1-4 Interrupt Functions The following methods can be used to circumvent this limitation: Method 1 All interrupt processing can be masked while the instruction is being exe- cuted. @INT(89) @PLS2(−−) DM 0010 @INT(89) Method 2 Execute the instruction again in the main program.
Page 46: Processing The Same Memory Locations With The Main Program And Interrupt Subroutines
Processing the Same Memory Locations with the Main Program and Interrupt Subroutines If a memory location is manipulated both by the main program and an inter- rupt subroutine, an interrupt mask must be set to disable interrupts. When an interrupt occurs, execution of the main program will be interrupted immediately, even during execution of an instruction.
Page 47 DM 0010. Therefore, in the comparison at point *1, the contents of DM 0000 and DM 0001 are not equal and processing stops with A in the OFF state. As a result, although the contents of DM 0000 and DM 0010 agree at the value...
Page 48: Input Interrupts
The INT(89) instruction determines which mode is used. In the Input Interrupt Mode, signals with a length of 100 µ s or more can be detected. In the Counter Mode, signals up to 1 kHz can be counted.
Page 49 Write 1 in the corresponding digit in DM 6628 to indicate that the input will be used as an input interrupt (input interrupt or counter mode.) b) Bits in DM 6630 through DM 6633 can be turned ON to cause the input to be refreshed before the interrupt subroutine is executed.
Page 50: Ladder
Section 1-4 Interrupt Functions 5. Program the associated program sections. a) Use INT(89) to refresh the counter SV in counter mode. (See page 28 for more details.) b) Write an interrupt subroutine within SBN(92) and RET(93) (only when using count-up interrupts.)
Page 51 (IR 000 to IR 015) Default: No input refresh Example If DM 6630 is set to 0100, IR 000 will be refreshed when a signal is received for interrupt 0. Note If input refreshing is not used, input signal status within the interrupt routine will not be reliable.
Page 52 If the bit corresponding to an input interrupt turns ON while masked, that input interrupt will be saved in memory and will be executed as soon as the mask is cleared. In order for that input interrupt not to be executed when the mask is cleared, the interrupt must be cleared from memory.
Page 53 Section 1-4 Interrupt Functions If the Counter Mode is not used, these SR bits can be used as work bits. 2. With the INT(89) instruction, refresh the Counter Mode set value and en- able interrupts. If D bits 0 to 3, which correspond to input interrupts 0 to 3, (@)INT(89) are set to "0,"...
Page 54 Section 1-4 Interrupt Functions Application Example In this example, input interrupt 0 is used in Input Interrupt Mode and input interrupt 1 is used in Counter Mode. Before executing the program, check to be sure the PC Setup. PC Setup: DM 6628: 0011 (IR 00000 and IR 00001 used for input interrupts) The default settings are used for all other PC Setup parameters.
Page 55: Masking All Interrupts
1-4-4 Masking All Interrupts The INT(89) instruction can be used to mask and unmask all interrupts as a group, including input interrupts, interval timer interrupts, and high-speed counter interrupts. The mask is in addition to any masks on the individual types of interrupts.
Page 56: Interval Timer Interrupts
2. Note 1. Interval timer 0 cannot be used when pulses are being output to a Transis- tor Output Unit by means of the SPED(64) instruction. 2. Interval timer 2 cannot be used at the same time as high-speed counter 0.
Page 57 Each time that the interval specified in word C + 1 elapses, the decrementing counter will decrement the present value by one. When the PV reaches 0, the designated subroutine will be called just once and the timer will stop.
Page 58 The time from when the interval timer is started until the execution of this instruction is calculated as follows: {(Contents of word C2) x (Contents of word C2 + 1) + (Contents of word C3)} x 0.1 ms If the specified interval timer is stopped, then “0000” will be stored.
Page 59: High-Speed Counter 0 Interrupts
Interrupt Functions Application Example In this example, an interrupt is executed every 2.4 ms (0.6 ms x 4) by means of interval timer 1. Assume the default settings for all of the PC Setup. (Inputs are not refreshed for interrupt processing.)
Page 60 Note The High-speed Counter 0 Reset Bit (SR 25200) is refreshed once every cycle, so in order for it to be read reliably it must be ON for at least one cycle. The “Z” in “phase-Z” is an abbreviation for “Zero.” It is a signal that shows that...
Page 61 Once the count has equaled all of the target values in the table, the target value is set to the first target value in the table, which is again compared to the current counted until the two values are equal.
Page 62 IR 00006 4. Make PC Setup settings in DM 6642. (See page 39 for more details.) a) Set 01 in the leftmost byte to indicate that high-speed counter 0 will be used. b) Set the input mode (differential phase mode or incrementing mode.) c) Set the reset method (phase-Z signal + software reset, or software re- set.)
Page 63 0. 0: Range condition not satisfied. 1: Range condition satisfied. Wiring Depending on the input mode, the input signals from the pulse encoder to the CPU Unit’s input terminal are as shown below. Terminal Allocated bit...
Page 64 Section 1-4 Interrupt Functions If the software reset is to be used, IR 00006 can be used as an ordinary input. Note 1. When the input mode is set to incrementing mode, IR 00005 can be used as an ordinary input.
Page 65 (i.e., during program execution) as long as no other table is saved. Reading the PV There are two ways to read the PV. The first is to read it from SR 230 and SR 231, and the second to use the PRV(62) instruction.
Page 66 There are two ways to change the PV of high-speed counter 0. The first way is to reset it by using the reset methods. (In this case the PV is reset to 0.) The second way is to use the INI(61) instruction.
Page 67: High-Speed Counter 0 Overflows/Underflows
Differential phase mode: F003 2768 to 0003 2767 Incrementing Mode: 0000 0000 to 0006 5535 Note 1. The values given above are theoretical and assume a reasonably short cy- cle time. The values will actually be those that existed one cycle before the overflow/underflow existed.
Page 68 Section 1-4 Interrupt Functions 2. The 6th and 7th digits of high-speed counter 0’s PV are normally 00, but can be used as “Overflow/Underflow Flags” by detecting values beyond the allowable counting ranges. High-speed counter 0 can be reset as described in the previous section or it can be reset automatically by restarting program execution.
Page 69: Pulse Output Function
Standard pulses can be output from a Transistor Output Unit’s output using SPED(64). Pulses can be output from just one bit at a time. The duty factor of the pulse output is 50% and the frequency can be set from 20 Hz to 1 kHz. Transistor Output Unit =50% (0.5)
Page 70 Unit at a time. 1,2,3... 1. Determine the IR word (IR 100 to IR 115) to be used for the pulse output. 2. Wire the Transistor Output Unit. Wire the terminal corresponding to the bit that will actually be used in the selected word.
Page 71 Output Units. (The bit is specified in the first operand in SPED(64).) The content of DM 6615 (0000 to 0015) specifies output words IR 100 to IR 115. For example, if DM 6615 is set to 0002, pulses will be output to IR 102.
Page 72: Communications Functions
1. The Programmable Terminal’s Programming Console functions can be used, but pin 7 on the DIP switch must be ON. 2. Turn ON pin 7 of the CPU Unit’s DIP Switch when using the peripheral port for any device other than a Programming Console.
Page 73: Host Link And No-Protocol Communications Settings
<MONITOR> PASSWORD! This is because, in order to write data to the CPU Unit, the PT changed the operation mode from RUN mode to MONITOR mode. To continue operation using the Programming Console, it is necessary to input the password again.
Page 74 (DM 6650). Communications Settings When pin 5 of the CPU Unit’s DIP Switch is OFF and the settings in DM 6646 (DM 6646 and DM 6651) (or DM 6651) are enabled in DM 6645 (or DM 6650), these settings determine the transmission frame format and baud rate, as shown in the following dia- gram.
Page 75 No-protocol communications The delay is not used the first time data is sent from the PC. The delay will affect other sends only if the normal time for the send comes before the time set for the transmission delay has expired.
Page 76: Host Link Communications Settings And Procedures
Link communications. PC Setup Settings Be sure to write 00 in the leftmost digits of DM 6645 (RS-232C port) or DM 6650 (peripheral port) to specify Host Link communications. Other Host Link communications parameters are set in the rightmost two digits of DM 6645/DM 6650 and DM 6646/DM 6651.
Page 77 From the time this instruction is executed until the data transmission is com- plete, AR 0805 (or AR 0813 for the peripheral port) will remain OFF. It will turn ON again upon completion of the data transmission. The TXD(48) instruction does not provide a response, so in order to receive confirmation that the com- puter has received the data, the computer’s program must be written so that it...
Page 78: No-Protocol Communications Settings And Procedures
Specify whether or not a start code is to be set at the beginning of the data, and whether or not an end code is to be set at the end. Instead of setting the end code, it is possible to specify the number of bytes to be received before the reception operation is completed.
Page 79 256 bytes, N will be between 254 and 256 depending on the designations for start and end codes. If the number of bytes to be sent is set to 0000, only the start and end codes will be sent.
Page 80: One-To-One Data Links
25209. To reset the peripheral port, turn ON SR 25208. These bits will turn OFF automatically after the reset. The start code and end code are not included in AR 09 or AR 10 (number of bytes received). Application Example...
Page 81 The word used by each PC will be as shown in the following table, according to the settings for the master, slave, and link words. Set the link area to LR 00 to LR 15 if the CQM1H is being linked with a CPM1, CPM1A, CPM2A, or SRM1(-V2) PC.
Page 82: Nt Link 1:1 Mode Communications
IR 001 of each Unit will be reflected in IR 100 of the other Unit. Likewise, the status of the other Unit’s IR 001 will be reflected in IR 100 of each Unit. IR 001 is an input word and IR 100 is an output word...
Page 83: Calculating With Signed Binary Data
Signed binary data is manipulated using 2’s complements and the MSB of the one- or two-word data is used as the sign bit. The range of data that can be expressed using one or two words is thus as follows: •...
Page 84: Arithmetic Flags
The results of executing signed binary instructions is reflected in the arith- metic flags. The flags and the conditions under which it will turn ON are given in the following table. The flags will be OFF when these conditions are not met.
Page 85: Using Signed-Binary Expansion Instructions
The procedure to using the Programming Console to allocate function codes Codes is shown in the CQM1H Operation Manual. Be sure that pin 4 of the CQM1H’s DIP switch is turned ON to enable use of a user-set instruction table before performing this operation.
Page 86 Section 1-7 Calculating with Signed Binary Data 10000 CLC(41) ADB(50) 04D2 FF85 0457 MBS(−−) 0457 LR00 04BC 00148BE4 CLC(41) SBBL(−−) 00148BE4 HR50 00003039 00145BAB DBSL(−−) 00145BAB DM1000 FFFFFB2E FFFFFBC7 Result 000000E8 Remainder...
Page 87 Section 1-7 Calculating with Signed Binary Data...
Page 88: Inner Boards
2-1-5 Names and Functions ........
Page 89: High-Speed Counter Board
High-speed Counter Pulse Inputs 1 to 4 The High-speed Counter Board counts high-speed pulses from 50 to 500 kHz entering through ports 1 to 4, and performs tasks according to the number of pulses counted. Input Modes The following three Input Modes are available: •...
Page 90: Applicable Inner Board Slots
2-1-5 Names and Functions One High-speed Counter Board provides two connectors that accept high- speed pulse inputs. CN1 is used for inputs 1 and 2, and CN2 is used for inputs 3 and 4. CQM1H-CTB41 High-speed Counter Board Pulse input 1...
Page 91: Specifications
Specifications Instructions Instruction Meaning CTBL(63) Used to register target or range comparison tables or used to start comparisons for previously registered comparison tables. A table can be registered and comparison started with separate instruc- tions or the same instruction. INI(61) Used to start or stop comparison using registered comparison table or used to change the PV of a high-speed counter.
Page 92 Turns ON when an error occurs in an Inner Board mounted in slot 1 or slot 2. The error code for slot 1 is stored in AR 0400 to AR 0407 and the error code for slot 2 is stored in AR 0408 to AR 0415.
Page 93 Count frequency, Numeric Range Mode, and counter reset method of high-speed counter 4 (Refer to the explanation given above for high-speed counter 1.) Count Frequency, Numeric Range Mode, and Counter Reset Method of High-speed Counters Value Count frequency Numeric Range Mode...
Page 94: High-Speed Counters 1 To 4
Two phase signals (phase A and phase B) with phase difference multiples of 1x, 2x, or 4x are used together with a phase-Z signal for inputs. The count is incremented or decremented according to differences in the two phase sig- nals.
Page 95 0, it returns to the maximum value. The number of points on the ring is determined by setting the maximum value (i.e., the ring value) to a value between 1 and 8388607 BCD or between 1 and 7FFFFFFF Hex.
Page 96 • Phase-Z signal + software reset • Software reset Phase-Z Signal (Reset Input) + Software Reset The PV of the high-speed counter is reset in the first rising edge of the phase- Z signal after the corresponding High-speed Counter Reset Bit (see below) turns ON.
Page 97 Board, it does not make any difference if the target value is reached as a result of incrementing or decrementing the PV. Note With high-speed counter 0 in the CPU Unit or high-speed counter 1 or 2 on the Pulse I/O Board or Absolute Encoder Interface Board, the leftmost bit of the word containing the subroutine number in the comparison table deter- mines if target values are valid for incrementing or for decrementing the PV.
Page 98 Comparison values 1 through 48 and bit patterns 1 through 48 are registered in the target value table. Of bits 00 to 11 of each of these bit patterns, bits 0 to 7 are stored as internal output bits, and bits 08 to 11 are stored as external output bits.
Page 99 Of bits 0 to 11 of each of these bit patterns, bits 0 to 7 are stored as internal output bits, and bits 8 to 11 are stored as external output bits. As shown in the diagram below, the bits in the...
Page 100 External outputs 1 to 4 are controlled by ORs performed on corresponding bits (i.e., bits with the same bit number) in the comparison result bits 08 to 11 for high-speed counters 1 to 4. The user must determine which outputs should be turned ON for each possible comparison result and set the bit pat- terns so that the OR operations will produce the desired result.
Page 101 Section 2-1 High-speed Counter Board Using PRV(62) The status of high-speed counters 1 to 4 can be read using PRV(62) in the manner shown below. (@)PRV(62) P: Port specifier C: 001 D: First destination word High-speed counter Value specified in P...
Page 102 Reset methods: Phase Z + software reset; software reset Numeric Range Modes: Ring Mode or Linear Mode Form in which PV of high-speed counter data is stored: 8-digit BCD or 8-digit hexadecimal External output method: Sourcing or Sinking switching of transistor output Set input voltages (switches on Board).
Page 103 Transistor Outputs Flags indicated counter start/stop (IR 21212 to Sourcing/Sinking Bits 08 to 11 of IR 21215 or AR 0512 to AR 0515) and counter DM 6602/DM 6611 comparison start/stop (IR 21308 to IR 21311 or AR 0508 to AR 0511).
Page 104 Input Mode, Count Frequency, Numeric Range Mode, and Counter Reset Method High-speed counter 1 Slot 1: Bits 00 to 07 of DM 6640 Slot 2: Bits 00 to 07 of DM 6643 High-speed counter 2 Slot 1: Bits 08 to 15 of DM 6640 Slot 2: Bits 08 to 15 of DM 6643...
Page 105 The comparison operation will start when the bit corresponding to the high- speed counter in IR 21208 to IR 21211 for slot 1 or AR 0508 to AR 0511 for slot 2 is turned ON. It is necessary to have registered a comparison table beforehand.
Page 106 The PVs of high-speed counters 1 to 4 are stored in memory in the following way. The form in which the PV data is stored is determined by the setting of bits 00 to 03 of DM 6602 for slot 1, and DM 6611 for slot 2. The default setting is 8-digit hexadecimal.
Page 107 IR 238 Port 4 IR 239 Note These words are refreshed only once every cycle, so the value read may differ slightly from the actual PV. Using PRV(62) PRV(62) can also be used to read the PVs of high-speed counters 1 to 4.
Page 108 The Reset Bit is kept ON in the program so that the PV of the counter is reset on the phase Z signal after the last target value has been reached.
Page 109 DM 6643: 0003 (High-speed counter 1: Count frequency of 50 kHz; Linear Mode; phase-Z signal + software reset; Up/Down Mode). When the PV reaches 2500, IR 05000 will be turned ON and external output 1 will be turned ON. When the PV reaches 7500, IR 05001 will be turned ON and external output 2 will be turned ON.
Page 110 As shown in the following programming example, the frequency of the contact pulse output is changed from the value of 500 Hz set when CTBL(63) is exe- cuted to 200 Hz, 100 Hz, and then 0 Hz when IR 05000, IR 05001, and then IR 05002 turn ON.
Page 111 @SBS(91) IR 05002 turns ON. • SBN(92) 25313 (Always ON) • Subroutine 001 SPED (64) Sets continuous contact pulse output from output position 02 at 200 Hz and starts pulse output. #0020 • RET(93) RET(93) • SBN(92) 25313 (Always ON) •...
Page 112: Pulse I/O Board
PV falls within a specified comparison range. Pulse Outputs 1 and 2 Two 10 Hz to 50 kHz pulses can be output from port 1 and port 2. Both fixed and variable duty factors can be used.
Page 113: System Configuration
Mode; Mode 2: Deceleration + Independent Mode; Mode 3: Decel- eration + Continuous Mode. 2. The port modes for both ports 1 and 2 is always set to the same mode, i.e., either High-speed Counter Mode and Simple Positioning Mode. The mode cannot be set separately for each port.
Page 114: Applicable Inner Board Slot
Section 2-2 Pulse I/O Board 2-2-4 Applicable Inner Board Slot The Pulse I/O Board can only be mounted in slot 2 (right slot) of the CQM1H- CPU51/61 CPU Unit. Slot 1: NO Slot 2: OK Pulse I/O Board 2-2-5 Names and Functions The CQM1H-PLB21 Pulse I/O Board has a CN1 connector for pulse input 1 and pulse output 1, and a CN2 connector for pulse input 2 and pulse output 2.
Page 115: Specifications
Clearing interrupt masks Clears masks from interrupts. Relevant Flags and Control Bits for Pulse Inputs Bits for Slot 2 of Inner Board when Using Pulse I/O Board Word Bits Name Function IR 232 00 to 15...
Page 116 SR Area Flags Word Function SR 254 Inner Board Error Flag AR Area Flags Word Function AR 04 08 to 15 Error codes for Inner Board in slot 2 00 Hex: Normal 01,02 Hex: Hardware error 03 Hex: PC Setup error...
Page 117: Pulse Output Specifications
12 to 15 (Setting for pulse outputs.) Pulse Output Specifications Instructions Pulse outputs are controlled using the seven instructions shown in the follow- ing table. The table also shows the relationship between the instruction and the type of pulse output. Instruction...
Page 118 ACC(––) Enabled Enabled Enabled Enabled Enabled Enabled Mode 0 (see (see (see (Deceleration constant note) note) note) constant + Continuous) speed speed PWM(––) Enabled Note The number of pulses can be changed, but the direction cannot be changed.
Page 119 Section 2-2 Pulse I/O Board Relevant Flags and Control Bits (for Pulse Output) Bits for Slot 2 of Inner Board when Using Pulse I/O Board Word Bits Name Function IR 236 00 to 15 Port 1 PV word (rightmost four digits)
Page 120: High-Speed Counters 1 And 2
(AR 0514/AR 0614) PULS(65) or PLS2(−−) executed (when setting number of pulses). Note The status of the AR Area flags shown above may differ from the actual pulse output status due to the output frequency. Relevant PC Setup Settings Word...
Page 121 Mode change only) Processing Input Signals and Input Modes The Input Modes that can be used for high-speed counters 1 and 2 are deter- mined by the signal types. 1,2,3... 1. Differential Phase Mode (Counting Rate = 25 kHz): Two phase-difference 4x signals (phase A and phase B) and a phase-Z signal are used for inputs.
Page 122 Either the phase-Z signal + software reset or software reset alone may be used to reset the PV of the count. These resets operate in the same way as for high-speed counter 0 (the built-in high-speed counter). Refer to page 35 for details.
Page 123 Input Modes: Determine Input Mode, reset method, Differential Phase, Pulse/Direction, or Up/Down and Numeric Range. Reset methods: Phase Z + software reset or Software reset Numeric Range: Ring Mode or Linear Mode Check method: Determine settings for ports1 and 2 High-speed Counter Mode: (Determine interrupt specifications).
Page 124 Default: 0000 (High-speed Counter Mode) Note 1. When using high-speed counter 1 and 2 interrupts, the port must be set to High-speed Counter Mode. Although the PV of the high-speed counter can be read in Simple Positioning Mode, high-speed counter 1 and 2 interrupts...
Page 125 OFF and then ON again before executing the pro- gram. 3. If DM 6611 is used to set ports 1 and 2 to Simple Positioning Mode, it is possible to use the BCMP(68) instruction to check the contents of the PV words of high-speed counters 1 and 2 (IR 232 to IR 235) and use this in- formation in place of high-speed counter 1 and 2 interrupts.
Page 126 003: Range table registered only TB: Beginning word of comparison table If C is set to 000, then comparisons will be made using the target value method; if 001, they will be made using the range comparison method. In both cases the comparisons will begin after the comparison table is regis- tered.
Page 127 F8388608 to 08388607 00000000 to 0006499 To specify a negative number in Linear Mode, set F Hex in the leftmost digit. Reading Status of High-speed Counters 1 and 2 There are 2 ways to read the status of high-speed counters 1 and 2: •...
Page 128 The status of high-speed counters 1 and 2 can also be determined by execut- ing PRV(62). Specify high-speed counter 1 or 2 (P=001 or 002) and the desti- nation word D. The status information will be written to bits 00 and 01 of D. Bits 02 to 15 will be set to 0.
Page 129 Section 2-2 Pulse I/O Board In addition, the following data is stored for the comparison table: DM 0000: 0003 — Number of target values: 3 DM 0001: 2500 — Target value 1: 2,500 DM 0002: 0000 DM 0003: 0100 — Comparison 1 interrupt processing routine No.: 100 DM 0004: 7500 —...
Page 130: Functions
Duty factor variable between 1% to 99%. Stop pulse output: INI(61) duty factor) Unidirectional output only. Note When a stepping motor is connected to the pulse output of port 1 or 2, use a maximum frequency not exceeding 20 kHz. 2-2-9 Fixed Duty Factor Pulse Output The following is a description of the procedure for performing pulse outputs from ports 1 and 2 using a duty factor of 50%.
Page 131 Section 2-2 Pulse I/O Board Note Use INI(61) when pulse output has to be stopped immediately, as for an emer- gency stop, etc. Pulse output will not stop even if a SPED(64), PLS2(––), or ACC(––) signal turns input OFF. Only stop pulse output when it is actually being output. Confirm the status of pulse output using the Pulse Output In Progress Flag (AR0515/AR0615).
Page 132 Section 2-2 Pulse I/O Board Single-Phase Fixed Duty The following flowchart shows the procedure for using PULS(65) and Factor Pulse Outputs SPED(64) to perform single-phase fixed duty factor pulse outputs without acceleration or deceleration. Determine pulse output port. Pulse output port 1 or 2.
Page 133 Section 2-2 Pulse I/O Board Trapezoidal Pulse Output The following flowchart shows the procedure for using PLS2(––) to perform With Same Acceleration/ trapezoidal pulse outputs with the same acceleration/deceleration rate. Deceleration Simple Positioning Mode Determine port mode. (PLS2(−− ) cannot be used in High-speed Counter Mode .) Determine pulse output port.
Page 134 Simple Positioning Mode: Determine port mode. All functions of ACC(−−) can be used. High-speed Counter Mode: Modes 1 to 3 of ACC(−−) can be used; Mode 0 (Acceleration + Indepen- dent) is disabled. Port 1 or port 2. Determine pulse output port.
Page 135 Default: 0000 (High-speed Counter Mode) The instructions that can be used are limited by the Port Mode setting for ports 1 and 2 of the Pulse I/O Board. The Port Mode is specified in the PC Setup (DM 6611). Port Mode Setting and...
Page 136 Enabled Positioning Mode The setting in DM 6611 is read only when the CQM1H is started. If this setting is changed, the PC must be turned OFF and ON again to enable the new value. Operation Settings for Ports 1 and 2 (DM 6643 and DM 6644)
Page 137 @SPED(64) When IR 00002 turns ON, the pulse frequency from port 1 is changed to 500 Hz. #0050 The following diagram shows the frequency of pulse outputs from port 1 as the program is executed. Frequency 1.5 kHz 1.0 kHz 0.5 kHz...
Page 138 0 Hz. Note: Use INI(61) if it is necessary to force pulse output to stop, as in emergency situations. #0000 The following diagram shows the frequency of pulse outputs from port 1 as the program is executed. Frequency 1.5 kHz 1.0 kHz...
Page 139 Example 3: Using The following example shows PLS2(––) used to output 100,000 CW pulses PLS(––) to Accelerate/ from port 1. The frequency is accelerated to 10 kHz at approximately 500 Hz/ Decelerate the Frequency 4 ms and decelerated at the same rate.
Page 140 The following example shows Mode 1 of ACC(––) used to increase the fre- ACC(––) to Accelerate the quency of a pulse output from port 1. The frequency is accelerated from 1 kHz Frequency at a Specified to 20 kHz at approximately 500 Hz/4 ms.
Page 141 The following example shows Mode 2 of ACC(––) used decrease the fre- ACC(––) to Decelerate the quency of a pulse output from port 1. The 2-kHz pulse output is already in Frequency at a Specified progress in independent mode and stops automatically when the number of Rate and Stop Output pulses is reached.
Page 142: Variable Duty Factor Pulse Outputs
The following is the procedure for outputting pulses with varying duty factors (i.e., the ratio of the pulse ON time and the pulse cycle) from ports 1 and/or 2. This function can be used for various kinds of control outputs, such as light intensity output or speed control output to an inverter.
Page 143 PROGRAM Mode and make the following settings in the PC Setup. Operation Settings of Ports 1 and 2 Make the following settings to set port 1 (DM 6643) or port 2 (DM 6644) to variable duty factor pulse output mode. Ports 1 and 2 can be set separately.
Page 144 The following example shows PWM(––) used to start a 1.5 kHz pulse output from port 1 and then change the duty factor from 50% to 25%.The pulse out- put is then stopped with INI(61). Before running the program, check that the settings in the PC Setup are as follows: DM 6643: 1000 (variable duty factor pulse setting for port 1).
Page 145: Determining The Status Of Ports 1 And 2
Pulse Output Status Indicates whether pulses are being output. Flag (0: No output; 1: Output in progress.) In addition to the above, bits 0 and 1 store information about the status of the high-speed counter. All other bits are 0.
Page 146: Absolute Encoder Interface Board
Absolute Encoder Interface Board Section 2-3 Note When PRV(62) is used to read a port’s status, the most recent information will be read regardless of the PC’s cycle time. 2-2-12 Precautions When Using Pulse Output Functions The Pulse I/O Board divides the 500 kHz source clock by an integer value to generate an output pulse frequency.
Page 147: Functions
BCD Mode and 360 ° Mode. Resolutions One of the following can be set: 8 bits (0 to 255), 10 bits (0 to 1023), or 12 bits (0 to 4095). The resolution should be set to match that of the encoder con- nected.
Page 148: Applicable Inner Board Slots
Section 2-3 Absolute Encoder Interface Board 2-3-4 Applicable Inner Board Slots The Absolute Encoder Interface Board can only be mounted in slot 2 (right slot) of the CQM1-CPU51/61 CPU Unit. Slot 1: No Slot 2: OK Absolute Encoder Interface Board...
Page 149: Absolute Encoder Input Specifications
Used to register target or range comparison tables or to start comparisons for previously registered comparison tables. (@)INI(61) Used to start or stop comparison using registered comparison table or to change the PV of a high- speed counter. (@)PRV(62) Used to read the PV or status of a high-speed counter.
Page 150 (BCD) for port 1 The origin is compensated when the Compensation Origin Compensation Bit (SR 25201 Bit turns ON in for port 1, SR 25202 for port 2) is PROGRAM turned ON. The compensation value mode. DM 6612 00 to 15...
Page 151: High-Speed Counter Interrupts
0 ° and 359 ° . CTBL(63) settings are made in 5 ° units. The resolution of the binary gray code inputs to ports 1 and 2 must be one of the three resolutions listed in the following table. The table also shows the range of values associated with each resolution in each operating mode.
Page 152 Section 2-3 50 ° to 355 ° Based on the conversions in the range 5 ° to 45 ° given above, conversions for the remaining values are calculated as follows: Setting ( ° ) ÷ 45 ° = A with B( ° ) remaining.
Page 153: Absolute Encoder Interface Board
1 or 2 interrupts in a program. Absolute High-speed Counter Settings DM 6643 contains the settings for absolute high-speed counter 1, and DM 6644 contains the settings for absolute high-speed counter 2. These words determine the operating modes and resolution settings.
Page 154 1,2,3... 1. Set the absolute encoder to the desired origin location. 2. Make sure that pin 1 of the CQM1H CPU Unit’s DIP switch is OFF (en- abling Programming Devices to write DM 6144 through DM 6568), then switch the PC to PROGRAM mode.
Page 155 • Reading PVs from memory (IR 232 or IR 234) • Using PRV(62) Reading PVs from Memory The PVs of high-speed counters 1 and 4 are stored in the data area words as 8-digit BCDs, regardless of whether the Board is in BCD Mode or 360 ° Mode. Leftmost...
Page 156 Section 2-3 Absolute Encoder Interface Board Note These words are refreshed only once every cycle, so they may differ from the actual PV. Using PRV(62) PRV(62) is used to read the PVs of absolute high-speed counters 1 and 2. Specify absolute high-speed counter 1 or 2 in P (P=001 or 002).
Page 157 P: Port 001: Port 1 002: Port 2 D: First destination word The status of the specified high-speed counter is stored in bit 00 of D, as shown in the following table. Function Comparison Operation Flag (0: Stopped; 1: Running) Bits 01 to 15 are set to 0.
Page 158 No subroutine number DM 0021 0000 Lower limit #1 (0°) DM 0022 0000 Upper limit #1 (0°) Eighth range setting (Not used.) DM 0023 FFFF No subroutine number In 360° Mode, upper and lower limits are set in units of 5°.
Page 159 #0008 • RET(93) RET(93) The following diagram shows the relationship between the PV of absolute high-speed counter 1 and Range Comparison Result Flags AR 0500 to AR 0507 as the above instructions are executed. AR 0500 AR 0501 AR 0502...
Page 160: Analog Setting Board
2-4-2 Function Each of the values set using the four variable resistors located on the front of the Analog Settings Board is stored as a 4-digit BCD between 0000 and 0200 in the analog settings words (IR 220 to IR 223).
Page 161: Applicable Inner Board Slots
The value for this control is stored in IR 222. The value for this control is stored in IR 223. !Caution While the power is turned ON, the contents of IR 220 to IR 223 are constantly refreshed with the values of the corresponding controls. Be sure that these words are not written to from the program or a Programming Device.
Page 162: Analog I/O Board
The signal ranges that can be used for each of the four analog input points are –10 to +10 V, 0 to 5 V, and 0 to 20 mA. A separate range is set for each point. The settings in DM 6611 determine the signal ranges.
Page 163: Applicable Inner Board Slot
Section 2-5 Analog I/O Board 2-5-4 Applicable Inner Board Slot The Analog I/O Board can only be mounted in slot 2 (right slot) of the CQM1H-CPU51/61 CPU Unit. Slot 1: No Slot 2: OK 2-5-5 Names and Functions The Analog I/O Board has a CN1 connector for the four analog inputs and a CN2 connector for 2 analog outputs.
Page 164: Specifications
20 mA +10 V +5 V 10 mA Setting (12-bit binary data) 10 V 0 mA Setting (11-bit binary data) Applications Examples The Board uses no special instructions. MOV(21) is used to read analog input values and set analog output values.
Page 165 Analog input 4 usage selection 12 to 15 Not used. (Fixed at 0.) Note The level of the analog output signal is determined by the connected terminal, and there is no PC Setup setting. These settings are reflected in status at power ON.
Page 166: Serial Communications Board
Serial Communications Boards The Serial Communications Board is an Inner Board for the CQM1H-series PCs. One Board can be installed in Inner Board slot 1 of a CQM1H-series CPU Unit. The Board cannot be installed in slot 2. The Board provides two serial communications ports for connecting host com- puters, Programmable Terminals (PTs), general-purpose external devices, and Programming Devices (excluding Programming Consoles).
Page 167: Features
The Serial Communications Board is an option that can be mounted in the CPU Unit to increase the number of serial ports without using an I/O slot. It supports protocol macros (which are not supported by the ports built into the CPU Units), allowing easy connection to general-purpose devices that have a serial port.
Page 168: System Configuration
Console) No-protocol Host Link Note An NT-AL001-E Converting Link Adapter can be used to convert between RS- 232C and RS-422A/485. This Link Adapter requires a 5-V power supply. Power is provided by the RS-232C port on the Serial Communications Board when the Link Adapter is connected to it, but must be provided separately when connecting the Link Adapter to other devices.
Page 169 Serial Communications Board Section 2-6...
Page 170: Memory Areas
3-2-1 Input and Output Areas........3-2-2 Work Areas .
Page 171: Memory Area Structure
Input bits can be allocated to Input Units or I/O Units. (note 1) IR 015 IR 01515 The 16 bits in IR 000 are always allocated to the CPU Unit’s built-in inputs. Output area 256 bits IR 100 to IR 10000 to Output bits can be allocated to Output Units or I/O Units.
Page 172 Available in the CQM1H-CPU61 CPU Unit only. Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. A minimum 2,528 bits are available as work bits. Other bits can be used as work bits when they are not used for their allocated functions, so the total number of available work bits depends on the configuration of the PC.
Page 173: Ir Area
Units. They reflect the ON/OFF status of input and output signals. Input bits begin at IR 00000, and output bits begin at IR 10000. With the CQM1H, only IR 00000 through IR 01515 can be used as input bits and only IR 10000 through IR 11515 can be used as output bits.
Page 174 8-point Units One word allocated These bits are allocated. The unused input bits (08 to 15) cannot be used as work bits, but unused out- put bits (08 to 15) can be used as work bits. 16-point I/O Units One input word is allocated to each 16-point Input Unit and one output word is allocated to each 16-point Output Unit.
Page 175 32-point Output Unit. I/O points 0 to 15 of connec- tor pin A correspond to bits 00 to 15 of the first allocated word (n) and I/O points 0 to 15 of connector pin B correspond to bits 00 to 15 of the next allo- cated word (n+1).
Page 176 When an Expansion I/O Block is connected, words are allocated started with the CPU Block and then continuing in order to the Expansion I/O Block. Input words are allocated from IR 001 and output words are allocated from IR 100.
Page 177 Note 1. I/O words are not allocated to the I/O Control Unit or I/O Interface Unit. 2. I/O words are not allocated to the Analog Power Supply Unit, but it is count- ed as one of the mounted Units. I/O Capacity and...
Page 178 Section 3-2 IR Area I/O Words Required by I/O Units Name Model Input words Output words points (starting from (starting from IR 001) IR 100) DC Input CQM1-ID211 Units CQM1-ID111 CQM1-ID212 CQM1-ID112 CQM1-ID213 CQM1-ID214 AC Input CQM1-IA121 Units CQM1-IA221 Relay...
Page 179 Units CQM1-LSE02 CompoBus/S Master Unit CQM1-SRM21-V1 4, 2, or 1 4, 2, or 1 CompoBus/D I/O Link Unit CQM1-DRT21 Note A total of 5 words are required when the next 4 Modules (E3X-MA11, E3C- MA11, E2C-MA11, and E39-M11) are mounted.
Page 180: Flags/Bits For An Inner Board In Slot 1 (Ir 200 To Ir 215)
Reception Overflow Flag Sequence Abort Completion Flag Protocol macro IR 202 00 to 07 Port 1 Communicating with PT Flags (Bits 00 to 07 = PTs 0 to 7) NT Link in 1:N mode Repeat Counter PV (00 to FF hexadecimal)
Page 181 Port 1 Continuous Trace Start/Stop Bits Protocol macro Port 2 Port 1 Shot Trace Start/Stop Bits Port 2 Port 1 Echoback Disable Bit (Only used for modem control in protocol macro mode. See note.) Port 2 Port 1 Protocol Macro Executing Flag No-protocol or...
Page 182 Function Read/ Write IR 220 00 to 15 Analog SV 1: 0000 to 0200 (4-digit BCD) IR 221 00 to 15 Analog SV 2: 0000 to 0200 (4-digit BCD) IR 222 00 to 15 Analog SV 3: 0000 to 0200 (4-digit BCD)
Page 183: Flags/Bits For An Inner Board In Slot 2 (Ir 232 To Ir 243)
Section 3-2 IR Area 3-2-5 Flags/Bits for an Inner Board in Slot 2 (IR 232 to IR 243) High-speed Counter Board Flags/Bits Word Bits Name Function Read/ Write IR 232 00 to 15 High-speed PV (rightmost 4 digits) Contains the high-speed counter PV for Counter 1 each of the High-speed Counter Board’s...
Page 184: Flags/Bits For Communications Units
IR 090 00 to 14 Always 0 Local Node’s Data Link Participation Status 0: The local node not in the Data Link or Data Link is stopped. 1: The local node is participating in the Data Link. IR 091 00 to 07...
Page 185: Sr Area
These bits mainly serve as flags related to CQM1H operation. The following table provides details on the various bit functions. SR 244 to SR 247 can also be used as work bits when input interrupts are not used in Counter Mode.
Page 186 The error code (a 2-digit number) is stored here when an error occurs. The FAL number is stored here when FAL(06) or FALS(07) is executed. This byte is reset (to 00) by exe- cuting a FAL 00 instruction or by clearing the error from a Programming Device.
Page 187 Turns ON when an error occurs in an Inner Board mounted in slot 1 or slot 2. The error code for slot 1 is stored in AR 0400 to AR 0407 and the error code for slot 2 is stored in AR 0408 to AR 0415.
Page 188: Tr Area
Hold Bit when power is turned ON. When this setting has been made and the I/O Hold BIt is ON, the status of bits in the IR and LR areas will not be cleared when the power is turned ON.
Page 189: Ar Area
Inner Board. The following table has been split to show the functions of the shared flags (AR 00 to AR 04 and AR 07 to AR 27) and the flags unique to particular Inner Boards (AR 05 and AR 06.) With the exception of AR 23 (Power-off Counter), the status of AR words and bits is refreshed each cycle.
Page 190: Flags/Bits For Inner Boards (Ar 05 And Ar 06)
Section 3-6 AR Area 3-6-2 Flags/Bits for Inner Boards (AR 05 and AR 06) High-speed Counter Board Slot 2 Flags/Bits (AR 05 to AR 06) Word Bit(s) Function Operation AR 05 High-speed Counter 1 Reset Bit Z Phase and software reset...
Page 191 00 to 07 High-speed Counter 2 Range Comparison Flags Bit 00 ON: Counter PV satisfies conditions for comparison range 1 Bit 01 ON: Counter PV satisfies conditions for comparison range 2 Bit 02 ON: Counter PV satisfies conditions for comparison range 3...
Page 192: Shared Flags/Bits (Ar 07 To Ar 27)
Turns ON when a communications error occurs at the CPU Unit’s built-in RS-232C port. RS-232C Port Transmission Enabled Flag Valid only when host link or RS-232C communications are used at the CPU Unit’s built-in RS- 232C port. RS-232C Port Reception Completed Flag Valid only when RS-232C communications are used at the CPU Unit’s built-in RS-232C port.
Page 193 Turn ON for transfer from the Memory Cassette to the CPU Unit. Automatically turns OFF again when operation is complete. Memory Cassette Compare Bit Turn ON to compare the contents of the PC with the contents of the Memory Cassette. Automati- cally turns OFF again when operation is complete. Memory Cassette Comparison Results Flag...
Page 194 00 will be stored if an I/O UNIT OVER error has occurred.) AR 23 00 to 15 Power-off Counter (4 digits BCD) This is the count of the number of times that the power has been turned OFF. To clear the count, write “0000” from a Programming Device.
Page 195: Using The Clock
Function AR 24 Power-up PC Setup Error Flag Turns ON when there is an error in DM 6600 to DM 6614 (the part of the PC Setup area that is read at power-up). Startup PC Setup Error Flag Turns ON when there is an error in DM 6615 to DM 6644 (the part of the PC Setup area that is read at the beginning of operation).
Page 196: Lr Area
AR 2100 through AR 2107 (day of week). 3. Turn ON AR 2115 (Clock Set Bit) when the time set in step 2 is reached. The clock will start operating from the time that is set, and the Clock Stop Bit and Clock Set BIt will be turned OFF automatically.
Page 197: Timer/Counter Area
Section 3-8 Note Because the CPM1, CPM1A, CPM2A, and SRM1(-V2) PCs have a smaller LR area, the CQM1H’s link area setting (DM 6645) must be set to LR 00 to LR 15 when connecting 1:1 with one of these PCs.
Page 198 See 3-11 Using Memory Cassettes for details. Read/Write DM Area The read/write area has no particular functions assigned to it and can be used freely. It can be read and written from the program or Programming Devices.
Page 199: Em Area
The CQM1H PCs can be equipped with a clock by installing a Memory Cas- sette with a clock. There is an “R” at the end of the model number of Memory Cassettes with a built-in clock. See 3-6-4 Using the Clock for more details.
Page 200: Memory Cassette Capacity And Program Size
The data stored in a Memory Cassette is mainly the CPU Unit’s read-only DM, PC Setup, and program, as shown in the following table. All of this data is han- dled as a single unit; the 4 areas cannot be read, written, or compared individ- ually.
Page 201 Cassette only. In CQM1H-CPU11/21 CPU Units, the content of AR 1508 to AR 1515 is nor- mally 04. The content of AR 1500 to AR 1507 is normally 04 when a 4-Kword Memory Cassette is installed. The size of the program indicated in AR 15 does not include the NOP(00)
Page 202: Writing To The Memory Cassette
If the switch is ON (i.e., writing not enabled), then turn the CQM1H power supply OFF and remove the Memory Cassette before changing the switch. 2. Check to see that the CQM1H is in PROGRAM mode. If it is in either RUN or MONITOR mode, use a Programming Device to change the mode.
Page 203: Comparing Memory Cassette Contents
Procedure Use the following procedure. 1,2,3... 1. Check to see that the CQM1H is in PROGRAM mode. If it is in either RUN or MONITOR mode, use the Programming Device to change to PRO- GRAM mode. 2. Turn ON AR 1402 from the Programming Device. The contents of the...
Page 204: Ladder-Diagram Programming
Ladder Instructions ........
Page 205: Basic Procedure
Sheet and Appendix F Program Coding Sheet. 1,2,3... 1. Obtain a list of all I/O devices and the I/O points that have been assigned to them and prepare a table that shows the I/O bit allocated to each I/O de- vice.
Page 206: Basic Ladder Diagrams
A ladder diagram consists of one line running down the left side with lines branching off to the right. The line on the left is called the bus bar. The branch- ing lines are called instruction lines or rungs. Along the instruction lines are placed conditions that lead to other instructions on the right side.
Page 207: Mnemonic Code
The operands designated for any of the ladder instructions can be any bit in the IR, SR, HR, AR, LR, or TC areas. This means that the conditions in a lad- der diagram can be determined by I/O bits, flags, work bits, timers/counters, etc.
Page 208: Ladder Instructions
If the instruction requires no definer or bit operand, the operand column is left blank for first line. It is a good idea to cross through any blank data col- umn spaces (for all instruction words that do not require data) so that the data column can be quickly scanned to see if any addresses have been left out.
Page 209 When this is the only condition on the instruction line, the execution condition for the instruction at the right is ON when the condition is ON. For the LOAD instruction (i.e., a normally open condition), the execution condition would be ON when IR 00000 was ON;...
Page 210 LOAD NOT instruction; the rest of the conditions correspond to OR or OR NOT instructions. The following example shows three conditions which corre- spond in order from the top to a LOAD NOT, an OR NOT, and an OR instruc- tion. Again, each of these instructions requires one line of mnemonic code.
Page 211: Output And Output Not
00001 OUT NOT In the above examples, IR 10000 will be ON as long as IR 00000 is ON and IR 10001 will be OFF as long as IR 00001 is ON. Here, IR 00000 and IR 00001 would be input bits and IR 10000 and IR 10001 output bits assigned to the Units controlled by the PC, i.e., the signals coming in through the input points...
Page 212: Logic Block Instructions
OR. What we need is a way to do the OR (NOT)’s independently and then combine the results. To do this, we can use the LOAD or LOAD NOT instruction in the middle of an instruction line. When LOAD or LOAD NOT is executed in this way, the current execution condition is saved in special buffers and the logic process is repeated from the beginning.
Page 213 An ON execution condition would be pro- duced for the instruction at the right either when IR 00000 is ON and IR 00001 is OFF or when IR 00002 and IR 00003 are both ON. The operation of and...
Page 214 10000 Again, with the method on the right, a maximum of eight blocks can be com- bined. There is no limit to the number of blocks that can be combined with the first method. The following diagram requires OR LOAD instructions to be converted to mnemonic code because three pairs of conditions in series lie in parallel to each other.
Page 215 00007 10001 Although the following diagram is similar to the one above, block b in the dia- gram below cannot be coded without separating it into two blocks combined with OR LOAD. In this example, the three blocks have been coded first and...
Page 216 When working with complicated diagrams, blocks will ultimately be coded starting at the top left and moving down before moving across. This will gener- ally mean that, when there might be a choice, OR LOAD will be coded before AND LOAD.
Page 217 Section 4-3 Basic Ladder Diagrams The following diagram requires an OR LOAD followed by an AND LOAD to code the top of the three blocks, and then two more OR LOADs to complete the mnemonic code. 00000 00001 Address Instruction...
Page 218 Block c The first logic block instruction is used to combine the execution conditions resulting from blocks a and b, and the second one is to combine the execution condition of block c with the execution condition resulting from the normally closed condition assigned IR 00003.
Page 219: Coding Multiple Right-Hand Instructions
4-3-7 Coding Multiple Right-hand Instructions If there is more than one right-hand instruction executed with the same execu- tion condition, they are coded consecutively following the last condition on the instruction line. In the following example, the last instruction line contains one more condition that corresponds to an AND with IR 00004.
Page 220: Branching Instruction Lines
IL(03)). TR Bits The TR area provides eight bits, TR 0 through TR 7, that can be used to tem- porarily preserve execution conditions. If a TR bit is placed at a branching point, the current execution condition will be stored at the designated TR bit.
Page 221 IR 00004 and the second time for an AND with the inverse of the status of IR 00005. TR bits can be used as many times as required as long as the same TR bit is not used more than once in the same instruction block. Here, a new instruc- tion block is begun each time execution returns to the bus bar.
Page 222: Interlocks
• Instruction 2 Note TR bits are must be input by the user only when programming using mne- monic code. They are not necessary when inputting ladder diagrams directly because they are processed for you automatically. The above limitations on the number of branching points requiring TR bits, and considerations on methods to reduce the number of programming instructions, still hold.
Page 223: Jumps
00006 ILC(03) If IR 00000 is ON in the revised version of diagram B, above, the status of IR 00001 and that of IR 00002 would determine the execution conditions for instructions 1 and 2, respectively. Because IR 00000 is ON, this would pro- duce the same results as ANDing the status of each of these bits.
Page 224 A jump can be defined using jump numbers 01 through 99 only once, i.e., each of these numbers can be used once in a JUMP instruction and once in a JUMP END instruction. When a JUMP instruction assigned one of these num-...
Page 225: Controlling Bit Status
Although these instructions are used to turn ON and OFF output bits in the IR area (i.e., to send or stop output signals to external devices), they are also used to control the status of other bits in the IR area or in other data areas.
Page 226: Differentiate Up And Differentiate Down
In the following example, HR 0000 will be turned ON when IR 00002 is ON and IR 00003 is OFF. HR 0000 will then remain ON until either IR 00004 or IR 00005 turns ON. With KEEP, as with all instructions requiring more than one instruction line, the instruction lines are coded first before the instruction that they control.
Page 227: Work Bits (Internal Relays)
I/O bits and other dedicated bits cannot be used as works bits. All bits in the IR area that are not allocated as I/O bits, and certain unused bits in the AR area, are available for use as work bits.
Page 228 IR 10000 must be left ON continuously as long as IR 001001 is ON and both IR 00002 and IR 00003 are OFF, or as long as IR 00004 is ON and IR 00005 is OFF. It must be turned ON for only one cycle each time IR 00000 turns ON (unless one of the preceding conditions is keeping it ON continu- ously).
Page 229: Programming Precautions
Again, diagram A, below, must be drawn as diagram B. If an instruction must be continuously executed (e.g., if an output must always be kept ON while the program is being executed), the Always ON Flag (SR 25313) in the SR area can be used.
Page 230: Program Execution
Program execution is only one of the tasks carried out by the CPU Unit as part of the cycle time. Refer to SECTION 7 CPU Unit Operation and Processing...
Page 231: Indirectly Addressing The Dm And Em Areas
Note The contents of a word used as an indirect must be BCD and must not exceed the addressing range of the DM or EM area. If it is not BCD, a BCD error will occur. If the DM or EM area is exceeded, an indirect addressing error will occur.
Page 232: Instruction Set
Ladder Diagram Instructions ........
Page 233 5-20-10 SCALING – SCL(66) ........
Page 234 5-21-3 BCD ADD – ADD(30) ........
Page 235 5-30 Communications Instructions ........
Page 236: Notation
In this section, each instruction description includes its ladder diagram sym- bol, the data areas that can be used by its operands, and the values that can be used as definers. Details for the data areas are also specified by the oper- and names and the type of data required for each operand (i.e., word or bit...
Page 237 When an indirect DM address is specified, the designated DM word will con- tain the address of the DM word that contains the data that will be used as the operand of the instruction. If, for example, *DM 0001 was designated as the...
Page 238: Differentiated Instructions
DIFD(14). DIFU(13) operates the same as a differentiated instruction, but is used to turn ON a bit for one cycle. DIFD(14) also turns ON a bit for one cycle, but does it when the execution condition has changed from ON to OFF. Refer to 5-9-4 DIFFERENTIATE UP and DOWN –...
Page 239: Expansion Instructions
The following 18 function codes can be used for expansion instructions: Expansion Instructions 17, 18, 19, 47, 48, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 87, 88, and 89 The 74 expansion instructions that can be used are listed below, along with the default function codes that are assigned when the CQM1H is shipped.
Page 240: Coding Right-Hand Instructions
If an IR or SR address is used in the data column, the left side of the column is left blank. If any other data area is used, the data area abbreviation is placed on the left side and the address is placed on the right side.
Page 241 Note The mnemonics of expansion instructions are followed by “(––)” as the func- tion code to indicate that they must be assigned function codes by the user in the instructions table before they can be used in programming. Refer to page 18 for details.
Page 242: Instruction Tables
Even the expansion instructions with default function codes have been omitted from the following table and space has been provided so that you can write in the ones you will be using. Refer to the next page for details on expansion instructions.
Page 243: Expansion Instructions
REFRESH RECEIVE 5-7-2 Expansion Instructions The 74 expansion instructions that can be used are listed below, along with the default function codes that are assigned when the CQM1H is shipped. Refer to 1-4 Interrupt Functions for more details. Mnemonic Code...
Page 244 LINE TO COLUMN COM (@) COMPLEMENT COS (@) –– COSINE –– SIGNED BINARY COMPARE CPSL –– DOUBLE SIGNED BINARY COMPARE CTBL(@) COMPARISON TABLE LOAD DBS (@) –– SIGNED BINARY DIVIDE DBSL (@) –– DOUBLE SIGNED BINARY DIVIDE DEC (@) BCD DECREMENT DEG (@) ––...
Page 245: Int(89)
LOG (@) –– LOGARITHM MAX (@) –– FIND MAXIMUM MBS (@) –– SIGNED BINARY MULTIPLY MBSL (@) –– DOUBLE SIGNED BINARY MULTIPLY MCMP (@) MULTI-WORD COMPARE MCRO (@) MACRO MIN (@) –– FIND MINIMUM MLB (@) BINARY MULTIPLY MLPX (@)
Page 246: Sft 10
Code Words Name Page PRV (@) HIGH-SPEED COUNTER PV READ PULS (@) SET PULSES PWM (@) –– PULSE WITH VARIABLE DUTY FACTOR RAD (@) –– DEGREES TO RADIANS RECV (@) NETWORK RECEIVE SUBROUTINE RETURN ROL (@) ROTATE LEFT ROOT (@)
Page 247: Ladder Diagram Instructions
IR, SR, AR, HR, TIM/CNT, LR Limitations There is no limit to the number of any of these instructions, or restrictions in the order in which they must be used, as long as the memory capacity of the PC is not exceeded. Description These six basic instructions correspond to the conditions on a ladder diagram.
Page 248: Bit Control Instructions
AND LD and OR LD logically combine two execution conditions, the current one and the last unused one. In order to draw ladder diagrams, it is not necessary to use AND LD and OR LD instructions, nor are they necessary when inputting ladder diagrams directly, as is possible from the CX-Programmer.
Page 249: Output And Output Not - Out And Out Not
The length of time that a bit is ON or OFF can be controlled by combining the OUT or OUT NOT with TIM. Refer to Examples under 5-16-1 TIMER – TIM for details.
Page 250: Keep - Keep(11)
Examples The following examples demonstrate the difference between OUT and SET/ RSET. In the first example (Diagram A), IR 10000 will be turned ON or OFF whenever IR 00000 goes ON or OFF. In the second example (Diagram B), IR 10000 will be turned ON when IR 00001 goes ON and will remain ON (even if IR 00001 goes OFF) until IR 00002 goes ON.
Page 251: Differentiate Up And Down - Difu(13) And Difd(14
ON and the current execution condition is either ON or OFF, DIFU(13) will either turn the designated bit OFF or leave it OFF (i.e., if the designated bit is already OFF). The designated bit will thus never be ON for longer than one cycle, assuming it is executed each cycle (see Precau- tions, below).
Page 252: No Operation - Nop(00)
5-28-8 INTERRUPT CONTROL – INT(89). Example In this example, IR 10014 will be turned ON for one cycle when IR 00000 goes from OFF to ON. IR 10015 will be turned ON for one cycle when IR 00000 goes from ON to OFF.
Page 253: Il(02) And Ilc(03)
The interlock is in effect while 00000 is OFF. Notice that 01000 is not turned ON at the point labeled A even though 00001 has turned OFF and then back ON.
Page 254: Jump And Jump End - Jmp(04) And Jme(05)
When the execution condition for the first IL(02) is OFF, TIM 127 will be reset to 1.5 s, CNT 001 will not be changed, and 00502 will be turned OFF. When the execution condition for the first IL(02) is ON and the execution condition for the second IL(02) is OFF, TIM 127 will be executed according to the status of 00001, CNT 001 will not be changed, and 00502 will be turned OFF.
Page 255: User Error Instructions
In a jump, this means the next time the jump from JMP(04) to JME(05) is not made, i.e., if a bit is turned ON by DIFU(13) or DIFD(14) and then a jump is made in the next cycle so that DIFU(13) or DIFD(14) are skipped, the designated bit will remain ON until the next time the execution condition for the JMP(04) controlling the jump is ON.
Page 256: Step Instructions: Step Define And Step Start-Step(08)/Snxt(09)
(i.e., END(01), IL(02)/ILC(03), JMP(04)/JME(05), and SBN(92)) may not be included. STEP(08) uses a control bit in the IR or HR areas to define the beginning of a section of the program called a step. STEP(08) does not require an execution condition, i.e., its execution is controlled through the control bit.
Page 257 STEP(08) is executed without a control bit. STEP(08) without a control bit must be preceded by SNXT(09) with a dummy control bit. The dummy control bit may be any unused IR or HR bit. It cannot be a control bit used in a STEP(08).
Page 258: Timer And Counter Instructions
Section 5-16 Timer and Counter Instructions If IR or LR bits are used for control bits, their status will be lost during any power interruption. If it is necessary to maintain status to resume execution at the same step, HR bits must be used.
Page 259: Timer - Tim
TIM or CNT. An SV can be input as a constant or as a word address in a data area. If an IR area word assigned to an Input Unit is designated as the word address, the Input Unit can be wired so that the SV can be set externally through thumb- wheel switches or similar devices.
Page 260: Counter - Cnt
PV reaches zero and will remain ON until the counter is reset. CNT is reset with a reset input, R. When R goes from OFF to ON, the PV is reset to SV. The PV will not be decremented while R is ON. Counting down from SV will begin again when R goes OFF.
Page 261 SR area clock pulse bits. CNT 001 counts the number of times the 1-second clock pulse bit (SR 25502) goes from OFF to ON. Here again, IR 00000 is used to control the times when CNT is operating. Because in this example the SV for CNT 001 is 700, the Completion Flag for CNT 002 turns ON when 1 second x 700 times, or 11 minutes and 40 seconds have expired.
Page 262: Reversible Counter - Cntr(12)
When decremented from 0000, the present value is set to SV and the Com- pletion Flag is turned ON until the PV is decremented again. When incre- mented past the SV, the PV is set to 0000 and the Completion Flag is turned ON until the PV is incremented again.
Page 263: High-Speed Timer - Timh(15)
Timers in jumped program sections will not be reset when the execution con- dition for JMP(04) is OFF, but the timer will stop timing if jump number 00 is used. The timers will continue timing if jump numbers 01 through 99) are used.
Page 264: Totalizing Timer - Ttim
TTIM(––) accuracy is +0.0/–0.1 second. A TTIM(––) timer will time as long as its execute condition is ON until it reaches the SV or until RB turns ON to reset the timer. TTIM(––) timers will time only as long as they are executed every cycle, i.e., they do not time, but maintain the current PV, in interlocked...
Page 265 (Content of *EM/*DM word is not BCD, or the EM/DM area boundary has been exceeded.) Example The following figure illustrates the relationship between the execution condi- tions for a totalizing timer with a set value of 2 s, its PV, and the Completion Flag. 00000 Address Instruction Operands TTIM(−−)
Page 266: Interval Timer - Stim(69)
If C1 is 000 to 005, a constant greater than 0255 cannot be used for C3. If C1 is 006 to 008, constants and DM 6143 to DM 6655 cannot be used for C2 or C3. If C1 is 010 to 012, both C2 and C3 must be set to 000. Description...
Page 267 Timer and Counter Instructions Section 5-16 Note 1. Interval timer 0 cannot be used when a pulse output is being output by the SPED(64) instruction. 2. Interval timer 2 cannot be used when high-speed counter 0 operation has been enabled in DM 6642 of the PC Setup.
Page 268: Register Comparison Table - Ctbl(63)
1. The Pulse I/O Board and Absolute Encoder Interface Board must be in- stalled in slot 2. 2. When a Pulse I/O Board is being used, the mode for ports 1 and 2 must be set to high-speed counter mode in DM 6611 of the PC Setup. CTBL(63)
Page 269 Target Value Comparison For high-speed counter 0 in the CPU Unit, up to 16 target values can be regis- tered. A subroutine number (1 to 16) is also registered for each target value. For high-speed counters 1 and 2 on a Pulse I/O Board or Absolute Encoder Interface Board, up to 48 target values can be registered.
Page 270 The ring value specifies the number of points in the ring and the maximum count value (ring value = max. count value+1). The ring value can be 0 to 65, 000. Do not change the ring value while a comparison is in progress.
Page 271 There are flags in the AR area which indicate when a high-speed counter’s PV falls within one or more of the 8 ranges. The flags turn ON when a PV is within the corresponding range.
Page 272 Timer and Counter Instructions Section 5-16 ring value is 0 to 65,000. Do not change the ring value while a comparison is in progress. Ring value, lower 4 digits (BCD) Ring value setting TB+1 Ring value, upper 4 digits (BCD)
Page 273 10-bit (0 to 1023) 12-bit (0 to 4095) For higher values, find the converted value to the nearest 45 ° and add the remainder from the table. For example, to convert 145 ° into 8-bit resolution: 32 × 3 (for 135 ° ) + 7 (for 10 ° ) = 103.
Page 274 Registers a target value comparison table. Start comparison with INI(61). Registers a range comparison table. Start comparison with INI(61). When the PV agrees with a target value or falls within a specified range, a bit pattern is output to the allocated IR word. Refer to 1-4-6 High-speed Counter 0 Interrupts for more details on table comparison.
Page 275 Target values 1 to 48 and bit patterns 1 to 48 are stored in the comparison table. Bits 0 to 7 of the bit pattern are stored as the internal bit pattern. Bits 8 to 11 are stored as the external bit pattern, the logical OR of these bits is cal- culated for the four high-speed counters, and the result is output to external outputs 1 to 4.
Page 276 8-digit upper limit, as well as the bit pattern. The registered bit pattern is output to the allocated IR word when the PV falls within a given range. The High-speed Counter Board does not generate interrupts; the reg- istered bit pattern is reflected in the allocated IR word and at the external out- puts.
Page 277 4 external outputs. Register a lower limit, upper limit, and bit pattern for each range (1 to 16) in the range comparison table. Bits 0 to 7 of the bit pattern are stored as the internal bit pattern.
Page 278 The following diagram shows the structure of a range comparison table for use with high-speed counters 1 to 4 when set for ring counting. The ring value specifies the number of points in the ring and the maximum count value (ring value = max.
Page 279 When the High-speed Counter Board is installed in slot 1, the bit patterns are output to IR 208 through IR 211. When the Board is installed in slot 2, the bit patterns are output to IR 240 through IR 243.
Page 280: Mode Control - Ini(61)
Absolute high-speed counter 2 High-speed Counter High-speed counter 1 Board High-speed counter 2 High-speed counter 3 High-speed counter 4 The function of INI(61) is determined by the control data, C. (P1 and P1+1 contain the new high-speed counter PV when changing the PV.)
Page 281 If C is 002, INI(61) changes the high-speed counter’s PV to the 8-digit value in P1 and P1+1. The leftmost 4 digits are stored in P1+1 and the rightmost 4 dig- its are stored in P1. A hexadecimal value of F in the most significant digit of PV indicates that the PV is negative.
Page 282: High-Speed Counter Pv Read - Prv(62)
Pulse I/O Board pulse outputs 1 and 2. Note Pulse output can be stopped only when pulses are not currently being output. The Pulse Output Flag (AR 0515 or AR 0615) can be used to check pulse out- put status.
Page 283 (IR 230 and IR 231 for high-speed counter 0, IR 200 to IR 207 or IR 232 to IR 239 for high-speed counters 1 to 4), but the allocated IR words are refreshed just once each cycle while PRV(62) reads the most up-to-date values.
Page 284 The following table shows the function of bits in D for high-speed counters 1 and 2 or pulse outputs from ports 1 and 2 on a Pulse I/O Board. Bits not listed in the table are not used and will always be 0.
Page 285 Pulse I/O Board high-speed counters 1 and 2, or Absolute Encoder Interface Board absolute high-speed counters 1 and 2. Bits 00 through 07 of D contain the Comparison Result flags for ranges 1 to 8. (0: Not in range; 1: In range)
Page 286: Shift Instructions
IR, SR, AR, HR, LR Limitations E must be greater than or equal to St, and St and E must be in the same data area. If a bit address in one of the words used in a shift register is also used in an instruction that controls individual bit status (e.g., OUT, KEEP(11)), an error...
Page 287: Word Shift - Wsft(16)
IR, SR, AR, DM, EM, HR, LR Limitations St and E must be in the same data area, and E must be greater than or equal to St. DM 6144 to DM 6655 cannot be used for St or E.
Page 288: Arithmetic Shift Left - Asl(25)
When the execution condition is OFF, ASL(25) is not executed. When the exe- cution condition is ON, ASL(25) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one bit to the left, and shifts the status of bit 15 into CY.
Page 289: Rotate Left - Rol(27)
ON, ROL(27) shifts all Wd bits one bit to the left, shifting CY into bit 00 of Wd and shifting bit 15 of Wd into CY. 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 Precautions...
Page 290: One Digit Shift Left - Sld(74)
IR, SR, AR, DM, EM, HR, LR Limitations St and E must be in the same data area, and E must be greater than or equal to St. DM 6144 to DM 6655 cannot be used for St or E.
Page 291: One Digit Shift Right - Srd(75)
IR, SR, AR, DM, EM, HR, LR Limitations St and E must be in the same data area, and E must be less than or equal to DM 6144 to DM 6655 cannot be used for St or E. Description When the execution condition is OFF, SRD(75) is not executed.
Page 292 The data in the shift register will be shifted one bit in the direction indicated by bit 12, shifting one bit out to CY and the status of bit 13 into the other end whenever SFTR(84) is executed with an ON execution condition as long as the reset bit is OFF and as long as bit 14 is ON.
Page 293: Asynchronous Shift Register - Asft(17)
IR, SR, AR, DM, EM, HR, LR Limitations St and E must be in the same data area, and E must be greater than or equal to St. DM 6144 to DM 6655 cannot be used for St or E.
Page 294: Data Movement Instructions
Precautions TIM/CNT numbers cannot be designated as D to change the PV of the timer or counter. You can, however, easily change the PV of a timer or a counter by using BSET(71). Flags Indirectly addressed EM/DM word is non-existent.
Page 295: Move Not - Mvn(22)
ON, MVN(22) transfers the inverted content of S (spec- ified word or four-digit hexadecimal constant) to D, i.e., for each ON bit in S, the corresponding bit in D is turned OFF, and for each OFF bit in S, the corre- sponding bit in D is turned ON.
Page 296: Block Transfer - Xfer(70)
D: Starting destination word IR, SR, AR, DM, EM, HR, TIM/CNT, LR Limitations S and S+N must be in the same data area, as must D and D+N. DM 6144 to DM 6655 cannot be used for D. Description When the execution condition is OFF, XFER(70) is not executed. When the execution condition is ON, XFER(70) copies the contents of S, S+1, ..., S+N...
Page 297: Block Set - Bset(71)
IR, SR, AR, DM, EM, HR, TIM/CNT, LR Limitations St must be less than or equal to E, and St and E must be in the same data area. DM 6144 to DM 6655 cannot be used for St or E.
Page 298: Data Exchange - Xchg(73)
Example The following example shows how to use DIST(80) to copy #00FF to HR 10 + Of. The content of LR 10 is #3005, so #00FF is copied to HR 15 (HR 10 + 5) when IR 00000 is ON.
Page 299 When bits 12 to 15 of C=9, DIST(80) can be used for a stack operation. The other 3 digits of C specify the number of words in the stack (000 to 999). The content of DBs is the stack pointer.
Page 300: Data Collect - Coll(81)
When bits 12 to 15 of C=9, COLL(81) can be used for an FIFO stack opera- tion. The other 3 digits of C specify the number of words in the stack (000 to 999). The content of SBs is the stack pointer.
Page 301 When bits 12 to 15 of C=8, COLL(81) can be used for an LIFO stack opera- tion. The other 3 digits of C specify the number of words in the stack (000 to 999). The content of SBs is the stack pointer.
Page 302: Move Bit - Movb(82)
DM 0001 and DM 0005. DM 0000 acts as the stack pointer. When IR 00000 goes from OFF to ON, COLL(81) copies the content of DM 0005 (DM 0000 + 5) to IR 001. The content of the stack pointer (DM 0000) is then decremented by one.
Page 303: Move Digit - Movd(83)
ON, MOVB(82) copies the specified bit of S to the spec- ified bit in D. The bits in S and D are specified by Bi. The rightmost two digits of Bi designate the source bit; the leftmost two bits designate the destination bit.
Page 304: Transfer Bits - Xfrb
Di: 0031 Di: 0023 Flags At least one of the rightmost three digits of Di is not between 0 and 3. Indirectly addressed EM/DM word is non-existent. (Content of *EM/*DM word is not BCD, or the EM/DM area boundary has been exceeded.) 5-18-10 TRANSFER BITS –...
Page 305: Comparison Instructions
In the following example, XFRB(––) is used to transfer 5 bits from IR 020 and IR 021 to LR 00 and LR 01. The starting bit in IR 020 is D (13), and the start- ing bit in LR 00 is E (14), so IR 02013 to IR 02101 are copied to LR 0014 to LR 0102.
Page 306 The following example shows how to save the comparison result immediately. Saving CMP(20) Results If the content of HR 09 is greater than that of 010, 10200 is turned ON; if the two contents are equal, 10201 is turned ON; if content of HR 09 is less than that of 010, 10202 is turned ON.
Page 307 R is set, e.g., if the CD equals the content of TB, bit 00 is turned ON, if it equals that of TB+1, bit 01 is turned ON, etc. The rest of the bits in R will be turned OFF.
Page 308: Block Compare - Bcmp(68)
If CD is found to be within any of these ranges (inclusive of the upper and lower limits), the corresponding bit in R is set. The comparisons that are made and the corresponding bit in R that is set for each true compar- ison are shown below.
Page 309: Double Compare - Cmpl(60)
When the execution condition is OFF, CMPL(60) is not executed. When the execution condition is ON, CMPL(60) joins the 4-digit hexadecimal content of Cp1+1 with that of Cp1, and that of Cp2+1 with that of Cp2 to create two 8- digit hexadecimal numbers, Cp+1,Cp1 and Cp2+1,Cp2. The two 8-digit num- bers are then compared and the result is output to the GR, EQ, and LE flags in the SR area.
Page 310: Multi-Word Compare - Mcmp(19)
The following example shows how to save the comparison result immediately. Saving CMPL(60) Results If the content of HR 10, HR 09 is greater than that of 011, 010, then 10000 is turned ON; if the two contents are equal, 10001 is turned ON; if content of HR 10, HR 09 is less than that of 011, 010, then 10002 is turned ON.
Page 311: Signed Binary Compare - Cps
When the execution condition is OFF, CPS(––) is not executed. When the exe- cution condition is ON, CPS(––) compares the 16-bit (4-digit) signed binary contents in Cp1 and Cp2 and outputs the result to the GR, EQ, and LE flags in the SR area.
Page 312: Double Signed Binary Compare - Cpsl
Comparison Instructions Precautions Placing other instructions between CPS(––) and the operation which accesses the EQ, LE, and GR flags may change the status of these flags. Be sure to access them before the desired status is changed. Flags Indirectly addressed EM/DM word is non-existent.
Page 313 Cp1+1, Cp1 = Cp2+1, Cp2 Cp1+1, Cp1 > Cp2+1, Cp2 Example In the following example, the content of 103, 102 is less than that of DM 0021, DM 0020, so 10002 is turned ON and the other bits, 10000 and 10001, are turned OFF.
Page 314: Area Range Compare - Zcp(- -)
ON, ZCP(––) compares CD to the range defined by lower limit LL and upper limit UL and outputs the result to the GR, EQ, and LE flags in the SR area. The resulting flag status is shown in the following table.
Page 315: Double Area Range Compare - Zcpl
Section 5-19 Comparison Instructions Example In the following example, the content of IR 002 (#6FA4) is compared to the range #0010 to #AB1F. Since #0010 ≤ #6FA4 ≤ #AB1F, the EQ flag and IR 10001 are turned ON. 00000 ZCP(−−)
Page 316: Conversion Instructions
ON, ZCPL(––) compares the 8-digit value in CD, CD+1 to the range defined by lower limit LL+1,LL and upper limit UL+1,UL and out- puts the result to the GR, EQ, and LE flags in the SR area. The resulting flag status is shown in the following table.
Page 317: Binary-To-Bcd - Bcd(24)
DM 6144 to DM 6655 cannot be used for R. Description BCD(24) converts the binary (hexadecimal) content of S into the numerically equivalent BCD bits, and outputs the BCD bits to R. Only the content of R is changed; the content of S is left unchanged. Binary...
Page 318: Double Bcd-To-Double Binary - Binl(58)
When the execution condition is OFF, BINL(58) is not executed. When the execution condition is ON, BINL(58) converts an eight-digit number in S and S+1 into 32-bit binary data, and outputs the converted data to R and R+1. S + 1...
Page 319: 4-To-16 Decoder - Mlpx(76)
ON, MLPX(76) converts up to four, four-bit hexadecimal digits from S into decimal values from 0 to 15, each of which is used to indi- cate a bit position. The bit whose number corresponds to each converted value is then turned ON in a result word.
Page 320 Example The following program converts digits 1 to 3 of data from DM 0020 to bit posi- tions and turns ON the corresponding bits in three consecutive words starting with HR 10. Digit 0 is not converted.
Page 321: 16-To-4 Encoder - Dmpx(77)
ON bit number, then transfers the hexadecimal value to the specified digit in R. The digits to receive the results are specified in Di, which also specifies the number of digits to be encoded.
Page 322 When 00000 is ON, the following diagram encodes IR words 010 and 011 to the first two digits of HR 10 and then encodes LR 10 and 11 to the last two digits of HR 10. Although the status of each source word bit is not shown, it is assumed that the bit with status 1 (ON) shown is the highest bit that is ON in the word.
Page 323: 7-Segment Decoder - Sdec(78)
Any or all of the digits in S may be converted in sequence from the designated first digit. The first digit, the number of digits to be converted, and the half of D to receive the first 7-segment display code (rightmost or leftmost 8 bits) are designated in Di.
Page 324 Section 5-20 Conversion Instructions are designated than remain in S (counting from the designated first digit), fur- ther digits will be used starting back at the beginning of S. Digit Designator The digits of Di are set as shown below.
Page 325 Conversion Instructions Example The following example shows the data to produce an 8. The lower case letters show which bits correspond to which segments of the 7-segment display. The table underneath shows the original data and converted code for all hexadec- imal digits.
Page 326: Ascii Convert - Asc(86)
8-bit ASCII code and places it into the destination word(s) begin- ning with D. Any or all of the digits in S may be converted in order from the designated first digit. The first digit, the number of digits to be converted, and the half of D to receive the first ASCII code (rightmost or leftmost 8 bits) are designated in Di.
Page 327 Parity The leftmost bit of each ASCII character (2 digits) can be automatically adjusted for either even or odd parity. If no parity is designated, the leftmost bit will always be zero. When even parity is designated, the leftmost bit will be adjusted so that the total number of ON bits is even, e.g., when adjusted for even parity, ASCII “31”...
Page 328: Ascii-To-Hexadecimal - Hex
All source words must be in the same data area. Bytes in the source words must contain the ASCII code equivalent of hexa- decimal values, i.e., 30 to 39 (0 to 9) or 41 to 46 (A to F). DM 6144 to DM 6655 cannot be used for D.
Page 329 The leftmost bit of each ASCII character (2 digits) is automatically adjusted for either even or odd parity. With no parity, the leftmost bit should always be zero. With odd or even parity, the leftmost bit of each ASCII character should be adjusted so that there is an...
Page 330: Scaling - Scl(66)
Example In the following example, the 2nd byte of LR 10 and the 1st byte of LR 11 are converted to hexadecimal values and those values are written to the first and second bytes of IR 010.
Page 331 (A ) and (B Value after conversion (BCD) Value before conversion (Hexadecimal) The results can be calculated by first converting all values to BCD and then using the following formula. Results = B – [(B – A )/(B –...
Page 332: Signed Binary To Bcd Scaling - Scl2
If the result is negative, then CY is set to 1. If the result is less than –9999, then –9999 is written to R. If the result is greater than 9999, then 9999 is writ- ten to R.
Page 333: Bcd To Signed Binary Scaling - Scl3
When 05000 is turned ON in the following example, the signed binary source data in 001 (#FFE2) is converted to BCD according to the parameters in DM 0000 to DM 0002. The result (#0018) is then written to LR 00 and CY is turned ON because the result is negative.
Page 334 Parameter words P1+3 and P1+4 define upper and lower limits for the result. If the result is greater than the upper limit in P1+3, then the upper limit is writ- ten to R. If the result is less than the lower limit in P1+4, then the lower limit is written to R.
Page 335 DM 0000 to DM 0004. The result is then writ- ten to DM 0100. (In the second conversion, the signed binary equivalent of –1035 is less than the lower limit specified in DM 0004, so the lower limit is written to DM 0100.)
Page 336: Hours-To-Seconds - Sec
IR, SR, AR, DM, EM, HR, TIM/CNT, LR 000: No function Limitations S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and S+1 must be BCD and must be in the proper hours/ minutes/seconds format.
Page 337: Seconds-To-Hours - Hms
IR, SR, AR, DM, EM, HR, TIM/CNT, LR 000: No function Limitations S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and S+1 must be BCD and must be between 0 and 35,999,999 seconds.
Page 338: Column-To-Line - Line
(S to S+15) to the 16 bits of word D (00 to 15). 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1...
Page 339: Line-To-Column - Colm
ON when the content of S is zero; otherwise OFF. Example The following example shows how to use COLM(––) to move the contents of word DM 0100 (00 to 15) to bit column 15 of the set (DM 0200 to DM 0215). 00000 Address Instruction Operands COLM(−−)
Page 340: 2'S Complement - Neg
S from 0000 and outputting the result to R; it will calculate the absolute value of negative signed binary data. If the content of S is 0000, the content of R will also be 0000 after execution and EQ (SR 25506) will be turned on.
Page 341: Double 2'S Complement - Negl
S+1 from $0000 0000 and outputting the result to R and R+1; it will calcu- late the absolute value of negative signed binary data. If the content of S is 0000 0000, the content of R will also be 0000 0000 after execution and EQ (SR 25506) will be turned on.
Page 342: Bcd Calculation Instructions
When the execution condition is OFF, ADD(30) is not executed. When the execution condition is ON, ADD(30) adds the contents of Au, Ad, and CY, and places the result in R. CY will be set if the result is greater than 9999. Au + Ad + CY Flags Au and/or Ad is not BCD.
Page 343: Bcd Subtract - Sub(31)
ON, SUB(31) subtracts the contents of Su and CY from Mi, and places the result in R. If the result is negative, CY is set and the 10’s com- plement of the actual result is placed in R. To convert the 10’s complement to the true result, subtract the content of R from zero (see example below).
Page 344 When 00002 is ON, the following ladder program clears CY, subtracts the con- tents of DM 0100 and CY from the content of 010 and places the result in HR If CY is set by executing SUB(31), the result in HR 10 is subtracted from zero (note that CLC(41) is again required to obtain an accurate result), the result is placed back in HR 10, and HR 1100 is turned ON to indicate a negative result.
Page 345: Bcd Multiply - Mul(32)
HR 10 2423 (0000 + (10000 – 7577)) CY 1 (negative result) In the above case, the program would turn ON HR 1100 to indicate that the value held in HR 10 is negative. 5-21-5 BCD MULTIPLY – MUL(32) Operand Data Areas...
Page 346: Bcd Divide - Div(33)
Example When IR 00000 is ON with the following program, the contents of IR 013 and DM 0005 are multiplied and the result is placed in HR 07 and HR 08. Example data and calculations are shown below the program.
Page 347: Double Bcd Add - Addl(54)
When the execution condition is OFF, DIV(33) is not executed and the pro- gram moves to the next instruction. When the execution condition is ON, Dd is divided by Dr and the result is placed in R and R + 1: the quotient in R and the remainder in R + 1.
Page 348 The rightmost 8 digits of the two numbers are added using ADDL(54), i.e., the contents of LR 00 and LR 01 are added to DM 0010 and DM 0011 and the results is placed in HR 10 and HR 11. The second addition adds the leftmost 4 digits of each number using ADD(30), and includes any carry from the first addition.
Page 349: Double Bcd Subtract - Subl(55)
ON, SUBL(55) subtracts CY and the 8-digit contents of Su and Su+1 from the 8-digit value in Mi and Mi+1, and places the result in R and R+1. If the result is negative, CY is set and the 10’s complement of the actual result is placed in R.
Page 350: Double Bcd Multiply - Mull(56)
IR, SR, AR, DM, EM, HR, TIM/CNT, LR MULL(56) @MULL(56) Mr: First multiplier word (BCD) IR, SR, AR, DM, EM, HR, TIM/CNT, LR R: First result word IR, SR, AR, DM, EM, HR, LR Limitations DM 6141 to DM 6655 cannot be used for R.
Page 351: Double Bcd Divide - Divl(57)
ON, DIVL(57) the eight-digit content of Dd and D+1 is divided by the content of Dr and Dr+1 and the result is placed in R to R+3: the quotient in R and R+1, the remainder in R+2 and R+3.
Page 352: Square Root - Root(72)
When the execution condition is OFF, ROOT(72) is not executed. When the execution condition is ON, ROOT(72) computes the square root of the eight- digit content of Sq and Sq+1 and places the result in R. The fractional portion is truncated.
Page 353: Binary Calculation Instructions
When the execution condition is OFF, ADB(50) is not executed. When the exe- cution condition is ON, ADB(50) adds the contents of Au, Ad, and CY, and places the result in R. CY will be set if the result is greater than FFFF. Au + Ad + CY ADB(50) can also be used to add signed binary data.
Page 354: Binary Subtract - Sbb(51)
ON, SBB(51) subtracts the contents of Su and CY from Mi and places the result in R. If the result is negative, CY is set and the 2’s com- plement of the actual result is placed in R.
Page 355: Binary Multiply - Mlb(52)
LR 00 and CY are subtracted from the content of IR 002 and the result is written to HR 01. CY is turned ON if the result is negative. If normal data is being used, a nega- tive result (signed binary) must be converted to normal data using NEG(––).
Page 356: Binary Divide - Dvb(53)
When the execution condition is OFF, DVB(53) is not executed. When the exe- cution condition is ON, DVB(53) divides the content of Dd by the content of Dr and the result is placed in R and R+1: the quotient in R, the remainder in R+1. Quotient...
Page 357: Double Binary Add - Adbl
R: First result word IR, SR, AR, DM, EM, HR, LR Limitations Au and Au+1 must be in the same data area, as must Ad and Ad+1, and R and R+1. DM 6142 to DM 6655 cannot be used for R.
Page 358: Double Binary Subtract - Sbbl
R: First result word IR, SR, AR, DM, EM, HR, LR Limitations Mi and Mi+1 must be in the same data area, as must Su and Su+1, and R and R+1. DM 6142 to DM 6655 cannot be used for R.
Page 359: Signed Binary Multiply - Mbs
(Content of *EM/*DM word is not BCD, or the EM/DM area boundary has been exceeded.) ON when the result is negative, i.e., when Mi is less than Su plus CY. ON when the result is 0. ON when the result exceeds +2,147,483,647 (7FFF FFFF).
Page 360: Double Signed Binary Multiply - Mbsl
MBS(––) multiplies the signed binary content of two words and outputs the 8- digit signed binary result to R+1 and R. The rightmost four digits of the result are placed in R, and the leftmost four digits are placed in R+1.
Page 361: Signed Binary Divide - Dbs
In the following example, MBSL(––) is used to multiply the signed binary con- tents of IR 101 and IR 100 with the signed binary contents of DM 0021 and DM 0020 and output the result to LR 24 through LR 01.
Page 362: Double Signed Binary Divide - Dbsl
Description DBS(––) divides the signed binary content of Dd by the signed binary content of Dr, and outputs the 8-digit signed binary result to R+1 and R. The quotient is placed in R, and the remainder is placed in R+1.
Page 363: Special Math Instructions
DBS(––) divides the 32-bit (8-digit) signed binary data in Dd+1 and Dd by the 32-bit signed binary data in Dr+1 and Dr, and outputs the 16-digit signed binary result to R+3 through R. The quotient is placed in R+1 and R, and the remainder is placed in R+3 and R+2.
Page 364 D+1. The address is identified differently for the DM area: 1,2,3... 1. For an address in the DM area, the word address is written to C+1. For ex- ample, if the address containing the maximum value is DM 0114, then #0114 is written in D+1.
Page 365: Find Minimum - Min
D+1. The address is identified differently for the DM area: 1,2,3... 1. For an address in the DM area, the word address is written to C+1. For ex- ample, if the address containing the minimum value is DM 0114, then #0114 is written in D+1.
Page 366: Average Value - Avg
When the execution condition is OFF, AVG(––) is not executed. Each time that AVG(––) is executed, the content of S is stored in words D+2 to D+N+1. On the first execution, AVG(––) writes the content of S to D+2; on the second execution it writes the content of S to D+3, etc.
Page 367: Sum - Sum(--)
The 3 rightmost digits of C must be BCD between 001 and 999. DM 6143 to DM 6655 cannot be used for D. If bit 14 of C is OFF (setting for BCD data), all data within the range R +N–1 must be BCD.
Page 368 Addition Units Words will be added if bit 13 is OFF and bytes will be added if bit 13 is ON. If bytes are specified, the range can begin with the leftmost or rightmost byte of R .
Page 369: Arithmetic Process - Apr
When the execution condition is OFF, APR(––) is not executed. When the exe- cution condition is ON, the operation of APR(––) depends on the control word If C is #0000 or #0001, APR(––) computes sin( θ ) or cos( θ )*. The BCD value of S specifies θ in tenths of degrees.
Page 370 Section 5-23 Special Math Instructions Examples Sine Function The following example demonstrates the use of the APR(––) sine function to calculate the sine of 30 ° . The sine function is specified when C is #0000. Address Instruction Operands 00000 APR(−−)
Page 371 12 line segments. The block of data is continuous, as it must be, from DM 0000 to DM 0026 (C to C + (2 × 12 + 2)). The input data is taken from IR 010, and the result is output to IR 011.
Page 372: Floating-Point Math Instructions
Section 5-24 Floating-point Math Instructions In this case, the input data word, IR 010, contains #0014, and f(0014) = #0726 is output to R, IR 011. $1F20 $0F00 (x,y) $0726 $0402 (0,0) $0005 $0014 $001A $05F0 5-24 Floating-point Math Instructions The Floating-point Math Instructions convert data and perform floating-point arithmetic operations.
Page 373 It isn’t necessary for the user to be aware of the IEEE754 data format when reading and writing floating-point data. It is only necessary to remember that...
Page 374 Example 31 30 23 22 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sign: –...
Page 375 Floating-point Math Instructions NaN (not a number) is produced when the result of calculations, such as 0.0/ 0.0, ∞ / ∞ , or ∞ – ∞ , does not correspond to a number or infinity. The exponent will be 255 (2 –...
Page 376 Section 5-24 Floating-point Math Instructions P (100, 100) θ DM 0000 DM 0200 DM 0001 DM 0201 DM 0200 DM 0202 DM 0201 DM 0204 DM 0202 DM 0202 DM 0206 DM 0204 DM 0204 DM 0208 DM 0206 DM 0208...
Page 377: Floating To 16-Bit: Fix(--)
. The result is then output to DM 0213 and DM 0212 as floating-point data. 3. In order to find the angle θ , Floating-point Math Instructions are used to –1 calculate tan (y/x). ATAN(––) outputs the result in radians, so DEG(––) is used to convert to degrees.
Page 378: Floating To 32-Bit: Fixl
ON if the data in S+1 and S is not a number (NaN). ON if the integer portion of S+1 and S is not within the range of –32,768 to 32,767. ON if the result is 0000.
Page 379: 16-Bit To Floating: Flt
ON if the data in S+1 and S is not a number (NaN). ON if the integer portion of S+1 and S is not within the range of –2,147,483,648 to 2,147,483,647. ON if the result is 0000 0000.
Page 380: 32-Bit To Floating: Fltl
ON, FLTL(––) converts the 32-bit signed binary value in S+1 and S to 32-bit floating-point data (IEEE754-format) and places the result in R+1 and R. A single 0 is added after the decimal point in the floating-point result.
Page 381 See note 2. –∞ See note 2. 1. The results could be zero (including underflows), a numeral, + ∞ , or – ∞ . Note 2. The Error Flag will be turned ON and the instruction won’t be executed. Flags Indirectly addressed EM/DM word is non-existent.
Page 382: Floating-Point Subtract: -F
+∞ See note 2. See note 2. 1. The results could be zero (including underflows), a numeral, + ∞ , or – ∞ . Note 2. The Error Flag will be turned ON and the instruction won’t be executed. Flags Indirectly addressed EM/DM word is non-existent.
Page 383: Floating-Point Multiply: *F
See note 2. +/–∞ –∞ +∞ See note 2. 1. The results could be zero (including underflows), a numeral, + ∞ , or – ∞ . Note 2. The Error Flag will be turned ON and the instruction won’t be executed.
Page 384: Floating-Point Divide: /F
ON if both the exponent and mantissa of the result are 0. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. (The result will be output as ±∞ .) ON if the absolute value of the result is too small to be expressed as a 32-bit floating-point value.
Page 385: Degrees To Radians: Rad
See note 2. See note 3. See note 3. See note 3. 1. The results could be zero (including underflows), a numeral, + ∞ , or – ∞ . Note 2. The results will be zero for underflows. 3. The Error Flag will be turned ON and the instruction won’t be executed.
Page 386: Radians To Degrees: Deg
Overflow Flag (SR 25404) will turn ON and the result will be output as ±∞ . If the absolute value of the result is less than the minimum value that can be expressed as floating-point data, the Underflow Flag (SR 25405) will turn ON and the result will be output as 0.
Page 387: Sine: Sin
ON if the source data is not recognized as floating-point data. ON if both the exponent and mantissa of the result are 0. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. (The result will be output as ±∞ .) ON if the absolute value of the result is too small to be expressed as a 32-bit floating-point value.
Page 388: Cosine: Cos
ON, COS(––) calculates the cosine of the angle (in radi- ans) expressed as a 32-bit floating-point value in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 for- mat.)
Page 389: Tangent: Tan
ON, TAN(––) calculates the tangent of the angle (in radi- ans) expressed as a 32-bit floating-point value in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 for- mat.)
Page 390: Arc Sine: Asin
The source data must be between –1.0 and 1.0. If the absolute value of the source data exceeds 1.0, an error will occur and the instruction won’t be exe- cuted. The result is output to words R+1 and R as an angle (in radians) within the range of – π /2 to π /2.
Page 391: Arc Cosine: Acos
ON, ACOS(––) computes the angle (in radians) for a cosine value expressed as a 32-bit floating-point number in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.)
Page 392: Arc Tangent: Atan
1.0, an error will occur and the instruction won’t be exe- cuted. The result is output to words R+1 and R as an angle (in radians) within the range of 0 to π . The following diagram shows the relationship between the input data and result.
Page 393 –1 Result (32-bit floating-point data) The result is output to words R+1 and R as an angle (in radians) within the range of – π /2 to π /2. The following diagram shows the relationship between the input data and result.
Page 394: Square Root: Sqrt
Source (32-bit floating-point data) Result (32-bit floating-point data) The source data must be positive; if it is negative, an error will occur and the instruction won’t be executed. If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag (SR 25404) will turn ON and the result will be output as + ∞...
Page 395: Exponent: Exp
Section 5-24 Floating-point Math Instructions ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. (The result will be output as + ∞ .) 5-24-18 EXPONENT: EXP(––) Operand Data Areas S: First source word...
Page 396: Logarithm: Log
ON if both the exponent and mantissa of the result are 0. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. (The result will be output as + ∞ .) ON if the absolute value of the result is too small to be expressed as a 32-bit floating-point value.
Page 397: Logic Instructions
ON if the source data is not recognized as floating-point data. ON if both the exponent and mantissa of the result are 0. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. (The result will be output as ±∞ .) 5-25 Logic Instructions 5-25-1 COMPLEMENT –...
Page 398: Logical And - Andw(34)
DM 6144 to DM 6655 cannot be used for R. Description When the execution condition is OFF, ANDW(34) is not executed. When the execution condition is ON, ANDW(34) logically AND’s the contents of I1 and I2 bit-by-bit and places the result in R. Example Flags Indirectly addressed EM/DM word is non-existent.
Page 399: Logical Or - Orw(35)
DM 6144 to DM 6655 cannot be used for R. Description When the execution condition is OFF, ORW(35) is not executed. When the execution condition is ON, ORW(35) logically OR’s the contents of I1 and I2 bit-by-bit and places the result in R. Example Flags Indirectly addressed EM/DM word is non-existent.
Page 400: Exclusive Nor - Xnrw(37)
Section 5-25 Logic Instructions Example Flags Indirectly addressed EM/DM word is non-existent. (Content of *EM/*DM word is not BCD, or the EM/DM area boundary has been exceeded.) ON when the result is 0. 5-25-5 EXCLUSIVE NOR – XNRW(37) Operand Data Areas...
Page 401: Increment/Decrement Instructions
Limitations DM 6144 to DM 6655 cannot be used for Wd. Description When the execution condition is OFF, INC(38) is not executed. When the exe- cution condition is ON, INC(38) increments Wd, without affecting Carry (CY). Precautions The content of Wd will be incremented every cycle if the undifferentiated form of INC(38) is used.
Page 402: Subroutine Instructions
The instructions within a subroutine are written in the same way as main program code. When all the subroutine instructions have been executed, control returns to the main program to the point just after the point from which the subroutine was entered (unless otherwise specified in the subroutine).
Page 403 RET(93) END(01) Flags A subroutine does not exist for the specified subroutine number. A subroutine has called itself. An active subroutine has been called. !Caution SBS(91) will not be executed and the subroutine will not be called when ER is...
Page 404: Special Instructions
TRSM(45) is used in the program to mark locations where specified data is to be stored in Trace Memory. Up to 12 bits and up to 3 words may be desig- nated for tracing. (Refer to the CX-Programmer Operation Manual for details.) TRSM(45) is not controlled by an execution condition, but rather by two bits in the AR area: AR 2515 and AR 2514.
Page 405 Programming Device. A positive or nega- tive delay can also be set to alter the actual point from which tracing will begin. Data can be recorded in any of three ways. TRSM(45) can be placed at one or more locations in the program to indicate where the specified data is to be traced.
Page 406: Message Display - Msg(46)
Appendix H for the ASCII codes. Japanese katakana characters are included in this code. If not all eight words are required for the message, it can be stopped at any point by inputting “OD.” When OD is encountered in a message, no more words will be read and the words that normally would be used for the mes- sage can be used for other purposes.
Page 407: I/O Refresh - Iorf(97)
To refresh I/O words, specify the first (St) and last (E) I/O words to be refreshed. When the execution condition for IORF(97) is ON, all words between St and E will be refreshed. This will be in addition to the normal I/O refresh performed during the CPU Unit’s cycle.
Page 408: Macro - Mcro(99)
ON, MCRO(99) copies the contents of I1 to I1+3 to IR 096 to IR 099, copies the contents of O1 to O1+3 to IR 196 to IR 199, and then calls and executes the subroutine specified in N. When the subroutine is completed, the contents of IR 196 through IR 199 is then transferred back to O1 to O1+3 before MCRO(99) is completed.
Page 409 (step 3 above). Note IR 096 to IR 099 and IR 196 to IR 199 can be used as work bits when MCRO(99) is not used.
Page 410: Bit Counter - Bcnt(67)
ON in all words between SB and SB+(N–1) and places the result in R. Flags N is not BCD, or N is 0; SB and SB+(N–1) are not in the same area. The resulting count value exceeds 9999. Indirectly addressed EM/DM word is non-existent.
Page 411 12 is ON. MSB LSB When bit 12 is OFF the bytes will be ORed in this order: 1, 2, 3, 4, ..When bit 12 is ON the bytes will be ORed in this order: 2, 3, 4, 5, ..
Page 412: Failure Point Detection - Fpd
IR, SR, AR, DM, EM, HR, LR Limitations D and D+8 must be in the same data area when bit 15 of C is ON. DM 6144 to DM 6655 cannot be used for T or D. C must be input as a constant.
Page 413 CY Flag if desired. 4. If bit 15 of C is ON, a preset message with up to 8 ASCII characters will be displayed on the Peripheral Device along with the bit address mentioned in step 2.
Page 414 Timer or counter number Note a) *For the TIM/CNT area, bit 09 of D+1 indicates whether the num- ber is a timer or counter. A 0 indicates a timer, and a 1 indicates a counter. b) The status of the leftmost bit of the bit number (bit 03) is reversed.
Page 415 FPD(––) is executed and begins monitoring when LR 0000 goes ON. If LR 0015 does not turn ON within 123.4 s and IR 10000 through IR 10003 are all ON, IR 10002 will be selected as the cause of the error, an FAL(06) error will be generated with an FAL number of 10, and the bit address and preset mes- sage (“10002–1ABC”) will be displayed on the Peripheral Device.
Page 416: Interrupt Control - Int(89)
This function is used to mask and unmask I/O interrupt inputs 00000 to Interrupts (CC=000) 00003. Masked inputs are recorded, but ignored. When an input is masked, the interrupt program for it will be run as soon as the bit is unmasked (unless it is cleared beforehand by executing INT(89) with CC=001).
Page 417 Set the corresponding bit in D to 1 to clear an I/O interrupt input. Bits 00 to 03 correspond to 00000 to 00003. Bits 04 to 15 should be set to 0.
Page 418: Set Pulses - Puls(65)
Output bits 00 to 15 (See note.) Port 1 Port 2 Note The bit between 00 and 15 that is output as the contact pulse is specified by the P operand in SPED(64), Control Data (C) The control data determines the direction of the pulse output to ports 1 and 2 and indicates whether the number of pulses and/or the deceleration point are specified in N to N+3.
Page 419 1 or port 2. Frequency Changes The number of pulses set to be output will be used even if SPED(64) is used to change the pulse frequency during operation. (The number of pulses can- not be changed during operation.)
Page 420: Speed Output- Sped(64)
Independent mode, frequency set in units of 1 Hz (See note.) Continuous mode, frequency set in units of 1 Hz (See note.) Note Settings of 002 and 003 can be specified only for ports 1 and 2 of a Pulse I/O Board (P=001 or P=002).
Page 421 (CW or CCW) as well. In independent mode, the number of pulses that have been output to ports 1 and 2 are contained in IR 236 and 237 (port 1) and IR 238 and IR 239 (port 2). Leftmost 4 digits Rightmost 4 digits...
Page 422 The pulse output cannot be used when interval timer 0 is operating. When a pulse output with a frequency of 500 Hz or higher is output from an output bit, set interrupt processing for the TIMH(15) TIM/CNT numbers 000 to 003 by setting #0104 in DM 6629 of the PC Setup.
Page 423: Pulse Output - Pls2
PLS2(––) is used to output a specified number of CW or CCW pulses from port 1 or 2. The pulse output accelerates to the target frequency at a specified rate and decelerates at the same rate. (Pulse output stops at 100 Hz.)
Page 424 The content of C determines the acceleration/deceleration rate. During accel- eration or deceleration, the output frequency is increased or decreased by the amount set in C every 4.08 ms. C must be BCD from 0001 to 0200 (10 Hz to 2 kHz).
Page 425: Acceleration Control - Acc
M always specifies the mode. Set P=001 or 002 to indicate port 1 or 2. Set M=000 to 003 to indicate modes 0 to Note Refer to 1-5 Pulse Output Function for more details.
Page 426 1,2,3... 1. The content of C determines the acceleration rate. During acceleration, the output frequency is increased by the amount set in C every 4.08 ms. C must be BCD from 0001 to 0200 (10 Hz to 2 kHz). 2. The content of C+1 specifies the frequency after acceleration. C+1 must be BCD from 0000 to 5000 (0 Hz to 50 kHz).
Page 427: Pulse With Variable Duty Factor - Pwm
IR, SR, AR, DM, EM, HR, TIM/CNT, LR, # Limitations PWM(––) cannot be used unless the PC Setup (DM 6643 or DM 6644) is set for variable duty factor pulse outputs. P must be 001 or 002 and F must be 000, 001, or 002.
Page 428: Data Search - Srch
DM 6643 to 1 to enable variable duty factor pulse output from port 1, and set the leftmost digit of DM 6644 to 1 to enable variable duty factor pulse output from port 2. It is not possible to output normal pulses from a port that is set for variable duty factor output.
Page 429 C+1. The address is identified differently for the DM area: 1,2,3... 1. For an address in the DM area, the word address is written to C+1. For ex- ample, if the lowest address containing the comparison data is DM 0114, then #0114 is written in C+1.
Page 430: Pid Control - Pid
PID(––) performs PID control based on the parameters specified in P1 through P1+6. The data in IW is used to calculate the output data that is writ- ten to OW. The following table shows the function of the parameter words.
Page 431: Network Instructions
!Caution Changes made to the parameters will not be effective until the execution con- dition for PID(––) goes from OFF to ON. Note Do not use PID(––) in the following situations; it may not be executed properly. In interrupt programs...
Page 432 Section 5-29 Network Instructions Limitations C through C+2 must be within the same data area and must be within the val- ues specified below. To be able to use SEND(90), the system must have a Controller Link Unit mounted. Description When the execution condition is OFF, SEND(90) is not executed.
Page 433 Network Instruction Error Flag (AR 0208) and Network Instruc- tion Enabled Flag (AR 0209) will be turned OFF, the Network Instruction Com- pletion Code will be set to 00, and the data will be sent to the node(s) on the network.
Page 434 DM 0100 to DM 0109 are trans- mitted to node number 3 in the local network where they are written to the ten words from DM 0200 to DM 0209. The data will be retransmitted up to 3 times if a response is not received within ten seconds.
Page 435: Network Receive - Recv(98)
IR, SR, AR, DM, EM, HR, TIM/CNT, LR Limitations C through C+2 must be within the same data area and must be within the val- ues specified below. To be able to use RECV(98), the system must have a Controller Link Unit mounted.
Page 436 END(01) is executed. A response is required with RECV(098) because the response contains the data being received, so set bit 13 of C+1 to “0” to indicate that a response is required. If the response hasn’t been received within the response monitoring time set in C+4, the request for data transfer will be retransmitted until a response is received or the specified number of retries (up to 15) is reached.
Page 437: Deliver Command: Cmnd
IR, SR, AR, DM, EM, HR, TIM/CNT, LR Limitations C through C+5 must be within the same data area and must be within the val- ues specified below. To be able to use CMND(––), the system must have a Controller Link Unit mounted.
Page 438 00: Response requested. 80: No response requested. Response monitoring time 0000: 2 s at 2 Mbps, 4 s at 1 Mbps, or 8 s at 500 Kbps 0001 to FFFF: 0.1 to 6,553.5 seconds (0.1 s units) Note 1. The allowed range is 01 to 20 hexadecimal (1 to 32) for a Controller Link, but the maximum node number will differ for other networks.
Page 439 The MEMORY AREA READ command reads 10 words from DM 0010 to DM 0019. The response contains the 2-byte command code (0101), the 2- byte completion code, and then the 10 words of data, for a total of 12 words or 24 bytes.
Page 440: Communications Instructions
D to D+(N ÷ 2)–1. Up to 256 bytes of data can be read at one time. If fewer than N bytes are received, the amount received will be read.
Page 441 RXD(47) instruction, setting communications protocol in the PC Setup, etc. The CQM1H will be incapable of receiving more data once 256 bytes have been received if received data is not read using RXD(47). Read data as soon as possible after the Reception Completed Flag is turned ON. The following table lists the Reception Completed Flags for the various ports.
Page 442: Transmit - Txd(48)
0: Port other than the peripheral port 1: Peripheral port The order in which data is written to memory depends on the value of digit 0 of C. Eight bytes of data 12345678... will be written in the following manner:...
Page 443 PC Setup, etc. Host Link Mode N must be BCD from #0000 to #0061 (i.e., up to 122 bytes of ASCII). The value of the control word (C) determines the port from which data will be out- put, as shown below.
Page 444: Change Serial Port Setup - Stup
MSB LSB When digit 0 of C is 0, the bytes of source data shown above will be transmit- ted in this order: 12345678... When digit 0 of C is 1, the bytes of source data shown above will be transmit- ted in this order: 21436587...
Page 445 Peripheral port (PC Setup: DM 6650 to DM 6654) If S is a word address, the contents of S through S+4 are copied to the 5 words in the PC Setup that contain the settings for the port specified by N.
Page 446 Enables the end code CR, LF. DM 0104 0000 Note An error will occur if STUP(––) is executed while a port’s Settings Changing Flag or Protocol Macro Executing Flag is ON, so include the flag as a nor- mally closed execution condition. 00000 20708 @STUP(−−)
Page 447: Protocol Macro - Pmcr
Serial Communications Board must be set to read or write word data when DM isn’t specified for S and R. If there is no send data, input the con- stant #0000 for S; any other constant or address specification will cause an error.
Page 448 S+1. Between 0 and 0128 words can be sent. If there is no send data, always set 0000 as a constant for S. An error will occur and the Error Flag will turn ON if any other constant or a word address is given and PMCR(––) will not be executed.
Page 449: Advanced I/O Instructions
PMCR(––) executes communications sequence 101 when IR 00000 is ON and SR 20708 (the Port 1 Protocol Macro Executing Flag) is OFF. DM 0100 contains 0003, so the next two words (DM 0101 and DM 0102) are used as the send data.
Page 450 Different from Output Unit 0007 If there are 8 digits of source data, they are placed in S and S+1, with the most significant digits placed in S+1. If there are 4 digits of source data, they are placed in S.
Page 451 O: Output word C: Control data If the first word holding the data to be displayed is specified at S, and the out- put word is specified at O, and the SV taken from the table below is specified at C, then operation will proceed as shown below when the program is exe- cuted.
Page 452: Digital Switch Input - Dsw(87)
IW and places the result in R. If the value is an 8-digit number, it is placed in R and R+1, with the most signif- icant digits placed in R+1. The number of digits is set in DM 6639 of the PC Setup.
Page 453 D0 through D3 from the digital switch to input points 0 through 3. In either case, output point 5 will be turned ON when one round of data is read, but there is no need to connect output point 5 unless required for the application.
Page 454 Number of digits to read 00: 4 digits 01: 8 digits Default: 4 digits Do not make any changes to bits 0 to 7. They are not related to DSW(87). Using the Instruction DSW(87) IW: Input word OW: Output word...
Page 455 HR51 DM0000 Note Output point 5 (here, IR 10005) turns on when one round of data is read and can be used to time switching the data storage area and gate signal (CS sig- nal) when DSW(87) is used to input data to different areas of memory.
Page 456: Hexadecimal Key Input - Hky
D+1 is lost. 2. The bits of D+2 and bit 4 of OW indicate key input. When one of the keys on the keypad (0 to F) is being pressed, the corresponding bit in D+2 (00 to 15) and bit 4 of OW are turned ON.
Page 457 Output Unit Input Unit The inputs can be connected to the input terminals on the CPU Unit or a DC Input Unit with 8 or more input points and the outputs can be connected from a Transistor Output Unit with 8 points or more.
Page 458 4. If more than eight digits are input, digits will be deleted beginning with the leftmost digit. 5. Input and output bits not used here can be used as ordinary input and out- put bits. With this instruction, one key input is read in 3 to 12 cycles. More than one cycle is required because the ON keys can only be determined as the outputs are turned ON to test them.
Page 459: Ten Key Input - Tky(18)
DM1000 and DM1001. IR 00015 is used as an “ENTER key,” and when IR 00015 turns ON, the num- bers stored in DM 1000 and DM 1001 are transferred to DM 0000 and DM 0001.
Page 460 Prepare a 10-key keypad, and connect it so that the switches for numeric keys 0 through 9 are input to points 0 through 9 as shown in the following diagram. Either the input terminals on the CPU Unit or the inputs on a DC Input Unit with 16 or more input points can be used.
Page 461 DM 1000 and DM 1001. Key information is stored in DM 1002. IR 00015 is used as an “ENTER key,” and when IR 00015 turns ON, the data stored in DM 1000 and DM 1001 will be transferred to DM 0000 and DM 0001.
Page 462: Host Link Commands
Communications Procedure ........
Page 463: Host Link Command Summary
Section 6-1 Host Link Command Summary Host Link Command Summary The Host Link commands listed in the following table can be sent to the CQM1H for Host Link communications. Header code PC mode Name Page Valid Valid Valid IR/SR AREA READ...
Page 464: End Codes
End Codes 6-2-1 Codes The response (end) codes listed in the following table are returned in the response frame for Host Link commands. When two or more errors occur, the end code for the first error will be returned. Contents...
Page 465 Section 6-2 End Codes A response will not be received with some errors, regardless of the command. These errors are listed in the following table. Error PC operation Parity, overrun, or framing error during com- The Communications Error Flag will be turned ON, an error code will be mand reception.
Page 466: Codes And Applicable Commands
End Codes Section 6-2 6-2-2 Codes and Applicable Commands The following table shows which end codes can be returned for each com- mand. Header Possible End Codes Comments No response No response No end code No end code...
Page 467: Communications Procedure
Commands from PC With CQM1H PCs, it is also possible in Host Link communications for the PC to send commands to the host computer. In this case it is the PC that has the transmission right and initiates the communications.
Page 468: Command And Response Formats
When commands are issued to the host computer, the data is transmitted in one direction from the PC to the host computer. If a response to a command is required, use a Host Link communications command to write the response from the host computer to the PC.
Page 469 Refer to the corresponding explanations under “Command Format.” Long Transmissions The largest block of data that can be transmitted as a single frame is 131 characters. A command or response of 132 characters or more must there- fore be divided into more than one frame before transmission. When a trans- mission is split, the ends of the first and intermediate frames are marked by a delimiter instead of a terminator.
Page 470 EXCLUSIVE OR performed on the data from the beginning of the frame until the end of the text in that frame (i.e., just before the FCS). Calcu- lating the FCS each time a frame is received and checking the result against the FCS that is included in the frame makes it possible to check for data errors in the frame.
Page 471: Commands From The Pc
In Host Link communications, commands are ordinarily sent from the host computer to the PC, but it is also possible for commands to be sent from the PC to the host computer. In Host Link Mode, any data can be transmitted from the PC to the host computer.
Page 472: Host Link Commands
This section explains the commands that can be issued from the host com- puter to the PC. 6-5-1 IR/SR AREA READ –– RR Reads the contents of the specified number of IR and SR words, starting from the specified word. Command Format ↵...
Page 473: Hr Area Read –– Rh
The response will be divided when reading more than 30 words of data. Parameters Read Data (Response) The number of present values specified by the command is returned in hexa- decimal as a response. The PVs are returned in order, starting with the speci- fied beginning timer/counter.
Page 474: Tc Status Read –– Rg
The contents of the number of words specified by the command are returned in hexadecimal as a response. The words are returned in order, starting with the specified beginning word. Note Be careful about the configuration of the DM area, as it varies depending on the CPU Unit model.
Page 475: Em Area Read –– Re
(0000 to 6143) (0001 to 6144) Note Input 00 Hex to specify bank number 0 or input two spaces to specify the cur- rent bank. Only the CQM1H-CPU61 CPU Unit has an EM area and it has only one bank, i.e., bank 0.
Page 476: Ir/Sr Area Write –– Wr
Parameter Write Data (Command) Specify in order the contents of the number of words to be written to the IR or SR area in hexadecimal, starting with the specified beginning word. Note The results will be as follows depending on the first write word.
Page 477: Hr Area Write –– Wh
Parameter Write Data (Command) Specify in order the contents of the number of words to be written to the HR area in hexadecimal, starting with the specified beginning word. Note If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed.
Page 478: Tc Status Write –– Wg
Specify the status of the Completion Flags, for the number of timers/counters to be written, in order (from the beginning word) as ON (i.e., “1”) or OFF (i.e., “0”). When a Completion Flag is ON, it indicates that the time or count is up.
Page 479: Em Area Write –– We
Write data (for number of words to write) Note Input 00 Hex to specify bank number 0 or input two spaces to specify the cur- rent bank. Only the CQM1H-CPU61 CPU Unit has an EM area and it has only one bank, i.e., bank 0.
Page 480: Ar Area Write –– Wj
TC number in the user’s program and reads the PV, which assumed to be set as a constant. The SV that is read is a 4-digit decimal number (BCD). The program is searched from the beginning, which may take as much as 10 seconds to produce a response.
Page 481 Note 1. The instruction specified under “Name” must be in four characters. 2. If the same instruction is used more than once in a program, only the first one will be read. 3. Use this command only when it is definite that a constant SV has been set.
Page 482 Section 6-5 Host Link Commands Operand, SV (Response) The name that indicates the SV classification is returned to “Operand,” and either the word address where the SV is stored or the constant SV is returned to “SV.” Operand Classification Constant or word address...
Page 483 (Space) COUNTER REVERSIBLE COUNTER Operand, SV (Response) The name that indicates the SV classification is returned to “Operand,” and either the word address where the SV is stored or the constant SV is returned to “SV.” Operand Classification Constant or...
Page 484 Section 6-5 Host Link Commands Parameters Name, TC Number (Command) In “Name,” specify the name of the instruction, in four characters, for changing the SV. In “TC number,” specify the timer/counter number used for the instruc- tion. Instruction name Classification...
Page 485 Note Only the CQM1H-CPU61 CPU Unit has an EM area. 6-5-22 SV CHANGE 3 –– W% Changes the contents of the second word of the TIM, TIMH(15), TTIM CNT, or CNTR(12) at the specified program address in the user’s program. With this command, program address can be specified for a program of up to 99,999 steps.
Page 486: Status Read –– Ms
Section 6-5 Host Link Commands Parameters Name, TC Number (Command) In “Name,” specify the name of the instruction, in four characters, for changing the SV. In “TC number,” specify the timer/counter number used for the instruc- tion. Instruction name Classification...
Page 487: Status Write –– Sc
Host Link Commands Parameters Status Data, Message (Response) “Status data” consists of four digits (two bytes) hexadecimal. The leftmost byte indicates CPU Unit operation mode, and the rightmost byte indicates the size of the program area. x 16 x 16...
Page 488: Error Read –– Mf
End code Error information Error information Terminator code (1st word) (2nd word) Parameters Error Clear (Command) Specify 01 to clear errors and 00 to not clear errors (BCD). Fatal errors can be cleared only when the PC is in PROGRAM mode.
Page 489: Forced Set –– Ks
ON: I/O Unit overflow (Error code E1) 6-5-26 FORCED SET –– KS Force sets a bit in the IR, SR, LR, HR, AR, or TC area. Just one bit can be force set at a time. Once a bit has been forced set or reset, that status will be retained until a FORCED SET/RESET CANCEL (KC) command or the next FORCED SET/ RESET command is transmitted.
Page 490: Forced Reset –– Kr
6-5-27 FORCED RESET –– KR Force resets a bit in the IR, SR, LR, HR, AR, or TC area. Just one bit can be force reset at a time.
Page 491: Multiple Forced Set/Reset –– Fk
6-5-28 MULTIPLE FORCED SET/RESET –– FK Force sets, force resets, or cancels the status of the bits in one word in the IR, SR, LR, HR, AR, or TC area.
Page 492: Forced Set/Reset Cancel –– Kc
Cancels all forced set and forced reset bits (including those set by FORCED SET, FORCED RESET, and MULTIPLE FORCED SET/RESET). If multiple bits are set, the forced status will be cancelled for all of them. It is not possible to cancel bits one by one using KC.
Page 493 Characters code Parameters Characters (Command, Response) For the command, this setting specifies any characters other than the carriage return (CHR$(13)). For the response, the same characters as specified by the command will be returned unaltered if the test is successful.
Page 494: Program Read –– Rp
Program data up to the maximum memory size. 6-5-34 COMPOUND COMMAND –– QQ Registers at the PC all of the bits, words, and timers/counters that are to be read, and reads the status of all of them as a batch.
Page 495 Read Word address, Data Format (Command) Depending on the area and type of data that are to be read, the information to be read is as shown in the following table. The “read data” is specified in four digits BCD, and the data format is specified in two digits BCD.
Page 496 (S): Space Data Break (Command) The read information is specified one item at a time separated by a break code (,). The maximum number of items that can be specified is 128. (When the PV of a timer/counter is specified, however, the status of the Completion Flag is also returned, and must therefore be counted as two items.)
Page 497: Txd Response –– Ex
↵ 6-5-37 TXD RESPONSE –– EX This is the response format used when the PC’s TXD(––) instruction is exe- cuted in Host Link mode. (TXD(––) converts the specified data into ASCII code and transmits it to the host computer with this format.) Response Format ↵...
Page 498: Cpu Unit Operation And Processing Time
I/O Response Time ........
Page 499: Cpu Unit Operation
Section 7-1 CPU Unit Operation Operation Flowchart The overall flow of CQM1H operation is as shown in the following flowchart. The time required to execute one cycle of CPU Unit operation is called the cycle time. Power application Is DIP switch...
Page 500: Power Interruptions
2. Outputs from all Output Units will be turned OFF. Note All outputs will turn OFF regardless of the status of the I/O Hold Bit or the set- ting of the I/O Hold Bit Status setting in the PC Setup.
Page 501 2. A power interruption may or may not be detected for a power interruption that lasts more than 10 ms but less than 25 ms for AC power supply, or more than 5 ms but less than 25 ms for DC power supply, i.e., the system may continue or it may stop.
Page 502: Startup Operation After A Power Interruption
The CPU Unit will start operating in RUN or MONITOR mode in any one of the following cases: • DM 6600 (Startup Mode) is at the default setting, nothing is connected to the peripheral port, and pin 7 on the DIP switch on the CPU Unit is ON.
Page 503: Cycle Time
Cycle time Operation conditions 10 ms or longer TIMH(15) may be inaccurate when TC 016 through TC 511 are used (operation will be normal for TC 000 through TC 015) (see note 1). 20 ms or longer Programming using the 0.02-second Clock Bit (SR 25401) may be inaccurate.
Page 504: Instruction Execution Times
1. The number of timers to undergo interrupt processing can be set in DM 6629 of the PC Setup. The default setting is for TC 000 through TC 015. 2. The PC Setup (DM 6655) can be used to disable detection of CYCLE TIME OVER error.
Page 505: Execution Times
The OFF execution time for an instruction can also vary depending on the circumstances, i.e., whether it is in an interlocked pro- gram section and the execution condition for IL is OFF, whether it is between JMP(04) and JME(05) and the execution condition for JMP(04) is OFF, or whether it is reset by an OFF execution condition.
Page 506 With 10-word shift register With 1,024-word shift register using *DM 1.7 ms With 6,144-word shift register using *DM 9.8 ms 20.1 When comparing a constant to a word 22.2 When comparing two words When comparing two *DM 58.0 17.7 When transferring a constant to a word 19.8...
Page 507 Word → word BCDL 45.7 *DM → *DM 79.2 XFER 54.7 When transferring a constant to a word 1.875 57.1 When transferring a word to a word When transferring 1,024 words using *DM 2.2 ms When transferring 6,144 words using *DM 12.5 ms...
Page 508 When decoding word to word 1.875 When decoding *DM to *DM 103.9 DIST 49.5 When setting a constant to a word + a word 1.875 52.0 When setting a word to a word + a word When setting *DM to *DM +*DM 108.3 75.8...
Page 509 Inputting 256 bytes via *DM 635.5 78.9 Outputting 1 byte via word (RS-232C) 1.875 Outputting 256 bytes via *DM (RS-232C) 624.3 64.7 Outputting 1 byte via word (host link) Outputting 256 bytes via *DM (host link) 106.4 CMPL 38.2 Comparing words 1.875 Comparing *DM...
Page 510 Stopping comparison via *DM 112.0 136.0 Changing PV via word Changing PV via *DM 154.0 High-speed counters 1 and 2 or pulse output from ports 1 and 2 on Pulse I/O Board: 267.2 Starting comparison via word Starting comparison via *DM 291.9 186.6...
Page 511 124.0 Designating output via word (reading PV) Designating output via *DM (reading PV) 142.0 High-speed counters 1 and 2 or pulse output from ports 1 and 2 on Pulse I/O Board: 206.4 Designating output via word (reading status) Designating output via *DM (reading status) 224.4...
Page 512 Conditions OFF execution time (µs) time (µs) CTBL High-speed counters 1 and 2 or pulse output from ports 1 and 2 on Pulse I/O 1.875 Board: 623.6 Target table with 1 target in words and start Target table with 1 target in *DM and start 649.3...
Page 513 21.4 Clear all interrupts via word Clear all interrupts via *DM 21.4 –– 413.2 Mode 0: Words for control words 1.875 Mode 0: *DM for control words 435.5 297.3 Mode 1: Words for control words Mode 1: *DM for control words 320.7...
Page 514 Code Mnemonic ON execution Conditions OFF execution time (µs) time (µs) –– 45.8 Computing sine 1.875 Linear approximation with 256-item table via *DM designation 348.0 Word → word –– ASIN 1.10 ms 1.875 *DM → *DM 1.13 ms Word → word ––...
Page 515 552.0 1.875 *DM → *DM 586.0 –– 44.8 Searching word, results to word 1.875 Searching 999 words via *DM, results to *DM 1.93 ms Constant × word → word –– 46.2 1.875 Word × word → word 48.6 *DM × *DM → *DM 104.0...
Page 516: I/O Response Time
The I/O response time is the time it takes after an input signal has been received (i.e., after an input bit has turned ON) for the PC to check and pro- cess the information and to output a control signal (i.e., to output the result of the processing to an output bit).
Page 517 Beginning of program Communications ports: Not used. Note The input ON delay for DC Input Units can be set in the PC Setup. Minimum I/O Response The CQM1H responds most quickly when it receives an input signal just prior Time to the input refresh phase of the cycle, as shown in the illustration below.
Page 518: One-To-One Link I/O Response Time
One-to-one Link I/O Response Time When two CQM1Hs are linked one-to-one, the I/O response time is the time required for an input executed at one of the CQM1Hs to be output to the other CQM1H by means of one-to-one link communications.
Page 519 The CQM1H takes the longest to respond under the following circumstances: Time 1,2,3... 1. The CQM1H receives an input signal just after the input refresh phase of the cycle. 2. The master to slave transmission does not begin on time.
Page 520: Interrupt Processing Time
Time 50 µs Interrupt input ON delay This is the delay time from the time the interrupt input bit turns ON until the time that the interrupt is executed. This is unrelated to other interrupts. ↓ (Interrupt condition realized.) (see note)
Page 521 Minimum response time: In addition to the response time shown above, the time required for executing the interrupt processing routine itself and a return time of 30 µ s must also be accounted for when returning to the process that was interrupted.
Page 522: Troubleshooting
Troubleshooting Flowcharts ........
Page 523: Introduction
Refer to SECTION 3 Memory Areas for lists of these. Note In addition to the errors described above, communications errors can occur when the PC is part of a Host Link System. Refer to SECTION 6 Host Link Commands for details. Programming Console Operation Errors The following error messages may appear when performing operations on the Programming Console.
Page 524: Programming Errors
Check level 0 checks for type A, B, and C errors; check level 1, for type A and B errors; and check level 2, for type A errors only.
Page 525: User-Defined Errors
60 to 69, 87, 88, and 89) are not subject to program checks. Program checks also do not cover DM 3070 to DM 6143 for PCs that do not support this part of the DM area (e.g., CQM1H-CPU11 and CQM1H-CPU21). Data will not be written even if these areas are specified and data read from these areas will always be undefined.
Page 526: Operating Errors
AR 1413 ON: The transfer destination is write-protected. If the PC is the destination, turn OFF the power to the PC, be sure that pin 1 of the CPU Unit’s DIP switch is OFF, clear the error, and transfer again.
Page 527 PLB21 is mounted). Check to see whether the device receiving the pulse output was affected. An error has been detected in the PC Setup. Check flags AR 2400 to AR 2402, and cor- rect as directed. AR 2400 ON: An incorrect setting was detected in the PC Setup (DM 6600 to DM 6614) when power was turned ON.
Page 528: Fatal Errors
Try to power-up again. MEMORY ERR AR 1611 ON: A checksum error has occurred in the PC Setup (DM 6600 to DM 6655). Initialize all of the PC Setup and reinput. AR 1612 ON: A checksum error has occurred in the program, indicating an incorrect instruction.
Page 529: Error Log
(3 words used.) DM6598 DM6599 Error records will be stored even if pin 1 on the DIP switch on the CPU Unit is turned ON to protect DM 6144 to DM 6655. For details about error codes refer to 8-5 Operating Errors.
Page 530: Troubleshooting Flowcharts
PC Setup for the error log. Note 1. If a Memory Cassette with a clock (RTC) is not used, the date and time of error occurrence will be “0000.” 2. Error will be recorded in the error log even if DM 6144 to DM 6655 are write-protected by turning ON pin 1 on the DIP switch on the front side of the CPU Unit.
Page 531 Is Power indicator lit? Tighten screws or Are there any loose replace wires. terminal screws or bro- ken wires? Is Power indicator lit? Replace the Power Supply Unit. Note Refer to CQM1H Operation Manual for the allowable voltage ranges for the CQM1H.
Page 532 Section 8-7 Troubleshooting Flowcharts Fatal Error Check The following flowchart can be used to troubleshoot fatal errors that occur while the Power indicator is lit. RUN indicator not lit. Is the ERR/ALM indicator lit? Determine the cause Is PC mode displayed...
Page 533 Non-fatal Error Check Although the PC will continue operating during non-fatal errors, the cause of the error should be determined and removed as quickly as possible to ensure proper operation. It may to necessary to stop PC operation to remove certain non-fatal errors.
Page 534 Section 8-7 Troubleshooting Flowcharts I/O Check The I/O check flowchart is based on the following ladder diagram section. (LS1) (LS2) 00002 00003 10500 SOL1 10500 SOL1 malfunction. Start (See note) Is the IR 10500 out- put indicator operat- ing normally? Check the voltage at the Wire correctly.
Page 535 Operation OK? Is terminal block making proper Operation OK? contact? Is input wiring correct? Check operation by using a dummy input signal to turn the input ON and OFF. Wire correctly. Tighten the terminal Replace terminal screws connector. Operation OK? Replace the Output Return to "start."...
Page 536 Consider using a temperature fan or cooler. below 55°C? Is the ambient Consider using a temperature above heater. 0°C? Is the ambient humidity Consider using an between 10% and air conditioner. 90%? Install surge pro- tectors or other Is noise being noise-reducing...
Page 538: Programming Instructions
A PC instruction is input either by pressing the corresponding Programming Console key(s) (e.g., LD, AND, OR, NOT) or by using function codes. To input an instruction with its function code, press FUN, the function code, and then WRITE. Refer to the pages listed programming and instruction details.
Page 539 Converts binary data in source word into BCD, and outputs converted data to result word. (@)ASL ARITHMETIC SHIFT Shifts each bit in single word of data one bit to left, with CY. LEFT (@)ASR ARITHMETIC SHIFT Shifts each bit in single word of data one bit to right, with CY.
Page 540 MOVE DIGIT Moves hexadecimal content of specified four-bit source digit(s) to specified destination digit(s) for up to four digits. (@)SFTR REVERSIBLE SHIFT Shifts data in specified word or series of words to either left or REGISTER right. (@)TCMP TABLE COMPARE Compares four-digit hexadecimal value with values in table consisting of 16 words.
Page 541 MACRO Calls and executes a subroutine replacing I/O words. Expansion Instructions The following table shows the instructions that can be treated as expansion instructions. The default function codes are given for instructions that have codes assigned by default. Code Mnemonic...
Page 542 Transmits a FINS command to the specified node(s) on the network and receives the response if necessary. (@)COLM LINE TO COLUMN Copies the 16 bits from the specified word to a bit column of 16 consecutive words. (@)COS COSINE Calculates the cosine of an angle (in radians) expressed as a 32-bit floating-point value.
Page 543 Page (@)NEGL DOUBLE 2’S COMPLE- Converts the eight-digit hexadecimal content of the source MENT words to its 2’s complement and outputs the result to R and R+1. PID CONTROL Performs PID control based on the specified parameters. (@)PLS2 PULSE OUTPUT Accelerates pulse output from 0 to the target frequency at a specified rate and decelerates at the same rate.
Page 544: Error And Arithmetic Flag Operation
ER indicates that operand data is not within requirements. CY indicates arithmetic or data shift results. GR indi- cates that a compared value is larger than some standard, LT that it is smaller, and EQ, that it is the same. EQ also indicates a result of zero for arithmetic operations.
Page 545 Appendix B Error and Arithmetic Flag Operation Mnemonic 25503 (ER) 25504 (CY) 25505 (GR) 25506 (EQ) 25507 (LE) 25404 (OF) 25405 (UF) Page XNRW(37) INC(38) DEC(39) STC(40) CLC(41) MSG(46) ADB(50) SBB(51) MLB(52) DVB(53) ADDL(54) SUBL(55) MULL(56) DIVL(57) BINL(58) BCDL(59) XFER(70)
Page 546 Appendix B Error and Arithmetic Flag Operation Expansion Instructions The default function codes are shown for the instructions that have default function codes. Mnemonic 25503 (ER) 25504 (CY) 25505 (GR) 25506 (EQ) 25507 (LE) 25404 (OF) 25405 (UF) Page 7SEG(88) ACC(––)
Page 547 Appendix B Error and Arithmetic Flag Operation Mnemonic 25503 (ER) 25504 (CY) 25505 (GR) 25506 (EQ) 25507 (LE) 25404 (OF) 25405 (UF) Page MCMP(19) MIN(––) NEG(––) NEGL(––) PID(––) PLS2(––) PMCR(––) PRV(62) PULS(65) PWM(––) RAD(––) RXD(47) SBBL(––) SCL(66) SCL2(––) SCL3(––) SEC(––) SIN(––)
Page 548: Memory Areas
IR area Input area 256 bits IR 000 to IR 00000 to Input bits can be allocated to Input Units or I/O Units. The 16 (note 1) IR 015 IR 01515 bits in IR 000 are always allocated to the CPU Unit’s built-in inputs.
Page 549 Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. A minimum 2,528 bits are available as work bits. Other bits can be used as work bits when they are not used for their allocated functions, so the total number of available work bits depends on the con- figuration of the PC.
Page 550 Sequence Abort Completion Flag Protocol macro IR 202 00 to 07 Port 1 Communicating with PT Flags (Bits 00 to 07 = PTs 0 to 7) NT Link in 1:N mode Repeat Counter PV (00 to FF hexadecimal) Protocol macro...
Page 551 Port 1 Continuous Trace Start/Stop Bits Protocol macro Port 2 Port 1 Shot Trace Start/Stop Bits Port 2 Port 1 Echoback Disable Bit (Only used for modem control in protocol macro mode. See note.) Port 2 Port 1 Protocol Macro Executing Flag No-protocol or...
Page 552 00 to 15 Analog SV 3: 0000 to 0200 (4-digit BCD) IR 223 00 to 15 Analog SV 4: 0000 to 0200 (4-digit BCD) Flags/Bits for an Inner Board in Slot 2 (IR 232 to IR 243) High-speed Counter Board Flags/Bits Word...
Page 553 Word Bits Function IR 232 00 to 15 Absolute Encoder High-speed Counter 1 PV (rightmost 4 digits) IR 233 00 to 15 Absolute Encoder High-speed Counter 1 PV (leftmost 4 digits) IR 234 00 to 15 Absolute Encoder High-speed Counter 2 PV (rightmost 4 digits)
Page 554 IR 090 00 to 14 Always 0 Local Node’s Data Link Participation Status 0: The local node not in the Data Link or Data Link is stopped. 1: The local node is participating in the Data Link. IR 091 00 to 07...
Page 555 These bits mainly serve as flags related to CQM1H operation. The following table provides details on the vari- ous bit functions. SR 244 to SR 247 can also be used as work bits, when input interrupts are not used in Counter Mode.
Page 556 The error code (a 2-digit number) is stored here when an error occurs. The FAL number is stored here when FAL(06) or FALS(07) is executed. This byte is reset (to 00) by exe- cuting a FAL 00 instruction or by clearing the error from a Programming Device.
Page 557 Turns ON when an error occurs in an Inner Board mounted in slot 1 or slot 2. The error code for slot 1 is stored in AR 0400 to AR 0407 and the error code for slot 2 is stored in AR 0408 to AR 0415.
Page 558 DM 6601 in the PC Setup can be set to maintain the previous status of the I/O Hold Bit when power is turned on. When this setting has been made and the I/O Hold BIt is ON, the status of bits in the IR and LR areas will not be cleared when the power is turned ON.
Page 559 01, 02: Hardware error PC Setup error PC stopped during pulse output or A/D (D/A) conversion error Flags/Bits for Inner Boards (AR 05 and AR 06) High-speed Counter Board Slot 2 Flags/Bits (AR 05 to AR 06) Word Bit(s) Function...
Page 560 Appendix C Memory Areas Pulse I/O Board Slot 2 Flags/Bits (AR 05 to AR 06) Word Bit(s) Operation AR 05 00 to 07 High-speed Counter 1 Range Comparison Flags Bit 00 ON: Counter PV satisfies conditions for comparison range 1...
Page 561 Turns ON when a communications error occurs at the CPU Unit’s built-in RS-232C port. RS-232C Port Transmission Enabled Flag Valid only when host link or RS-232C communications are used at the CPU Unit’s built-in RS- 232C port. RS-232C Port Reception Completed Flag Valid only when RS-232C communications are used at the CPU Unit’s built-in RS-232C port.
Page 562 Insufficient Capacity Flag Turns ON when transfer could not be executed due to insufficient capacity at the transfer destina- tion. No Program Flag Turns ON when transfer could not be executed due to there being no program in the Memory Cas- sette.
Page 563 Turns ON if the Memory Cassette is installed while the power is on. Memory Cassette Transfer Error Flag Turns ON if a transfer cannot be successfully executed when DIP switch pin No. 2 is set to ON (i.e., set to automatically transfer the contents of the Memory Cassette at power-up.)
Page 564 “0000” from a Programming Device. AR 24 Power-up PC Setup Error Flag Turns ON when there is an error in DM 6600 to DM 6614 (the part of the PC Setup area that is read at power-up). Startup PC Setup Error Flag Turns ON when there is an error in DM 6615 to DM 6644 (the part of the PC Setup area that is read at the beginning of operation).
Page 566: Using The Clock
The following illustration shows the configuration of the words (AR 17 through AR 21) that are used with the clock. These words can be read and used as required. (AR 17 is provided so that the hour and minute can be accessed quickly.)
Page 567 It is also possible, by using AR 2113, to simply set the seconds to “00” without going through a complicated procedure. When AR 2113 is turned ON, the clock time will change as follows: If the seconds setting is from 00 to 29, the seconds will be reset to “00” and the minute setting will remain the same.
Page 568: I/O Assignment Sheet
Appendix E I/O Assignment Sheet Name of system Produced by Verified by Authorized by PC model Sheet no. IR_____ Unit no.: Model: IR_____ Unit no.: Model: IR_____ Unit no.: Model: IR_____ Unit no.: Model:...
Page 570: Program Coding Sheet
Appendix F Program Coding Sheet Name of system Produced by Verified by Authorized by Chart no. Address Instruction Function Operands code...
Page 571 Appendix F Program Coding Sheet Address Instruction Function Operands code...
Page 572 Appendix F Program Coding Sheet Address Instruction Function Operands code...
Page 574: List Of Fal Numbers
Appendix G List of FAL Numbers Name of system Produced by Verified by Authorized by PC model Chart no. FAL contents Corrective measure FAL contents Corrective measure...
Page 575 Appendix G List of FAL Numbers FAL contents Corrective measure FAL contents Corrective measure...
Page 576: Extended Ascii
Appendix H Extended ASCII The following codes are used to output characters to the Programming Console or Data Access Console using MSG(46) or FPD(––). Refer to pages 381 and 387 for details. Right Left digit digit 0, 1, 8, 9 ”...
Page 578: Glossary
An operand that is used to designate the bit or bits of a word to be used by an instruction.
Page 579 Data that is stored in a memory of a PC and which is shared by other PCs in the same system. Each PC has a specified section(s) of the area allocated to it. Each PC writes to the section(s) allocated to it and reads the sections allo- cated to the other PCs with which it shares the common data.
Page 580 An operand that specifies how an instruction is to be executed. The control data may specify the part of a word is to be used as the operand, it may specify the destination for a data transfer instructions, it may specify the size of a data table used in an instruction, etc.
Page 581 A unit of storage in memory that consists of four bits. digit designator An operand that is used to designate the digit or digits of a word to be used by an instruction. DIN track A rail designed to fit into grooves on various devices to allow the devices to be quickly and easily mounted to it.
Page 582 ‘distributed’ over the system. Distributed control is a concept basic to PC Systems. DM area A data area used to hold only word data. Words in the DM area cannot be ac- cessed bit by bit. DM word A word in the DM area.
Page 583 A computer that is used to transfer data to or receive data from a PC in a Host Link system. The host computer is used for data management and overall sys- tem control. Host computers are generally small personal or business comput- ers.
Page 584 I/O Units include Input Units and Output Units, each of which is available in a range of specifications. I/O word A word in the IR area that is allocated to a Unit in the PC System and is used to hold I/O status for that Unit. IBM PC/AT or compatible A computer that has similar architecture to, that is logically compatible with, and that can run software designed for an IBM PC/AT computer.
Page 585: Ladder Diagram
A type of programming where execution moves directly from one point in a pro- gram to another, without sequentially executing any instructions in between. jump number A definer used with a jump that defines the points from and to which a jump is to be made. ladder diagram (program) A form of program arising out of relay-based control systems that uses circuit- type diagrams to represent the logic flow of programming instructions.
Page 586 An input that is normally closed, i.e., the input signal is considered to be present when the circuit connected to the input opens. negative delay A delay set for a data trace in which recording data begins before the trace sig- nal by a specified amount. nesting Programming one loop within another loop, programming a call to a subroutine within another subroutine, or programming one jump within another.
Page 587 The signal sent from the PC to an external device. The term output is often used abstractly or collectively to refer to outgoing signals. output bit A bit in the IR area that is allocated to hold the status to be sent to an output device. output device An external device that receives signals from the PC System.
Page 588 Changing the content of a memory location so that the previous content is lost. parity Adjustment of the number of ON bits in a word or other unit of data so that the total is always an even number or always an odd number. Parity is generally used to check the accuracy of data after being transmitted by confirming that the number of ON bits is still even or still odd.
Page 589 The portable form of Programming Device for a PC. Programming Device A Peripheral Device used to input a program into a PC or to alter or monitor a program already held in the PC. There are dedicated programming devices, such as Programming Consoles, and there are non-dedicated devices, such as a host computer.
Page 590 See terminal instruction. rightmost (bit/word) The lowest numbered bit of a group of bits, generally of an entire word, or the lowest numbered word of a group of words. This bit/word is often called the least-significant bit/word. rising edge The point where a signal actually changes from an OFF to an ON status.
Page 591 One or more words in which data is shifted a specified number of units to the right or left in bit, digit, or word units. In a rotate register, data shifted out one end is shifted back into the other end. In other shift registers, new data (either specified data, zero(s) or one(s)) is shifted into one end and the data shifted out at the other end is lost.
Page 592 The process of moving data from one location to another within the PC, or be- tween the PC and external devices. When data is transferred, generally a copy of the data is sent to the destination, i.e., the content of the source of the trans- fer is not changed.
Page 593 A switch used to write-protect the contents of a storage device, e.g., a floppy disk. If the hole on the upper left of a floppy disk is open, the information on this floppy disk cannot be altered.
Page 594: Index
ACC(– –) Controller Link System ADBL(– –) instructions address tracing converting See also tracing, data tracing. See also data, converting – Analog I/O Board counters components conditions when reset flags and bits creating extended timers installation...
Page 595 – floating-point math instructions DM area logarithms duty factor square roots fixed Frame Check Sequence pulse with variable duty factor See also frames, FCS variable frame checksum calculating with FCS(– –) frames dividing EC Directives xxiv precautions...
Page 596 I/O bits methods I/O points PC transmission refreshing procedures I/O refresh operations See also Host Link commands types data transfer I/O response time dividing frames one-to-one link communications frame See also timing definition I/O words...
Page 597 NOP(00) – DIFU(13) using in interlocks operands using in jumps DIST(80) combining with AND DIV(33) OR LD DIVL(57) combining with AND LD DMPX(77) use in logic blocks DSW(87) OR NOT DVB(53) ORW(35) END(01) EXP(– –) OUT NOT –F(– –) PID(– –) FAL(06) PLS2(–...
Page 598 SRD(75) overflows and overflows STC(40) programming STEP(08) high-speed counter 0 STH(– –) overflows and overflows STIM(69) high-speed counters 1 and 2 STUP(– –) input SUB(31) parameters SUBL(55) input interrupts SUM(– –) interval timers TAN(– –) scheduled interrupt mode...
Page 599: Floating-Point Math Instructions
AR area bits allowable designations DM area requirements EM area operating environment flags precautions flags and bits (SR area) HR area operations IR area bits effects on cycle time link bits internal processing structure flowchart timer and counter bits...
Page 600: Expansion
Host Link pulse outputs no-protocol determining status of ports 1 and 2 PC Setup fixed-duty-factor defaults flags and control bits expansion instructions from ports 1 and 2 high-speed counters 1 and 2...
Page 601 Index parameters See also See data tracing and address tracing. – PC Setup settings trigonometric functions pulse outputs arc cosine seven-segment displays arc sine converting data arc tangent converting degrees to radians signed binary arithmetic flags converting radians to degrees...
Page 602: Revision History
Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W364-E1-05 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version.

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Omron CQM1H - PROGRAM Programming Manual

Table of Contents

Precautions

Section 1

Section 2 Inner Boards

Section 3 Memory Areas

Section 4 Ladder-Diagram Programming

Section 5 Instruction Set

Instruction Set

Host Link Commands

CPU Unit Operation and Processing Time

Troubleshooting

Glossary

Index

Revision History

Quick Links

Chapters

Troubleshooting

Related Manuals for Omron CQM1H - PROGRAM

Summary of Contents for Omron CQM1H - PROGRAM