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I
n this chapter, we will introduce how to use the AVSTx8 configuration method to
load their design file from the flash memory device to the FPGA after the board
power on. As shown in
component of this configuration system. A Parallel Flash Loader II (PFL II) IP is
implemented in the System MAX 10 FPGA, allowing users to send bit stream files of
user's project from host to the System MAX 10 FPGA through the JTAG interface.
Then, the bit stream files will be written into the QSPI Flash connected to the System
MAX 10 FPGA via the PFL II IP. Batch file sof_2_pof.bat is designed to merge
factory.sof, user.sof, and option bit into a AVSTx8.pof file. Batch file program_pof.bat is
designed to program the AVSTx8.pof file into QSPI Flash.
After the user's bit stream files are stored into the QSPI Flash device, when the MA27
board is powered on, the PFL II IP in the System MAX 10 FPGA will automatically load
the bit stream file from the QSPI Flash first, and then configure the FPGA through the
Avalon-ST x8 interface.
In this chapter, we will introduce how to correctly set the FPGA to work in AVSTx8
mode, how to program bit stream files into the QSPI Flash, and how to switch the
image file to be loaded.
MA27
User Manual
QSPI-Flash
Programming
Figure
3-1, the System MAX 10 FPGA is the core
85
Chapter 3
www.terasic.com
February 17,
2024
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