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DDR4C_DBI_n1
DDR4C_DBI_n2
DDR4C_DBI_n3
DDR4C_DBI_n4
DDR4C_DBI_n5
DDR4C_DBI_n6
DDR4C_DBI_n7
DDR4C_DBI_n8
DDR4C_CS_n[0]
DDR4C_CS_n[1]
DDR4C_RESET_n
DDR4C_ODT[0]
DDR4C_ODT[1]
DDR4C_PAR
DDR4C_ALERT_n
DDR4C_ACT_n
DDR4C_EVENT_n
DDR4C_C[0]
DDR4C_C[1]
MA27
User Manual
[0]
Data Bus Inversion
[1]
Data Bus Inversion
[2]
Data Bus Inversion
[3]
Data Bus Inversion
[4]
Data Bus Inversion
[5]
Data Bus Inversion
[6]
Data Bus Inversion
[7]
Data Bus Inversion
[8]
Chip Select
Chip Select
Chip Reset
On Die
Termination
On Die
Termination
Command and
Address Parity
Input
Register ALERT_n
output
Activation
Command Input
Chip Temperature
Event
Chip ID
Chip ID
56
1.2V POD
1.2V POD
1.2V POD
1.2V POD
1.2V POD
1.2V POD
1.2V POD
1.2V POD
SSTL-12
SSTL-12
1.2 V
SSTL-12
SSTL-12
SSTL-12
1.2 V
SSTL-12
1.2 V
SSTL-12
SSTL-12
PIN_MD30
PIN_MD11
PIN_LR17
PIN_LR33
PIN_MD23
PIN_LR5
PIN_LR27
PIN_LB28
PIN_KF42
PIN_KF38
PIN_KU42
PIN_KU40
PIN_KR41
PIN_KJ39
PIN_KU32
PIN_KJ43
PIN_JY26
PIN_KC37
PIN_JY36
www.terasic.com
February 17,
2024
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