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Board
Signal Name
Reference
SW7.1
JTAG_INPUT
SW7.2
MAX_JTAG_ON
SW7.3
FPGA_BYPASS_n
SW7.4
HPS_BYPASS_n
PCIe Clock Select Switch
The PCIe Clock Select Switch is mainly used to control the reference clock source of
PCIe applications sent to FPGA transceivers.
reference clocks distribution on the board for PCIe applications. As shown in the figure,
MA27
User Manual
Table 2-5 JTAG Bypass Switch setting
If no external blaster is connected
to the External JTAG header (J7):
1 : The board's JTAG input interface is
from the on-board USB blaster II
0: The board's JTAG input interface is
from the PCIe EP Edge
1 : Enable the JTAG interface of the
System MAX10 FPGA into the JTAG
chain
0: Disable the JTAG interface of the
System MAX10 FPGA into the JTAG
chain
1 : Enable the JTAG interface of the
FPGA into the JTAG
chain
0: Disable the JTAG interface of the
FPGA into the JTAG
chain
1 : Enable the JTAG interface of the
HPS connector into the JTAG
chain
0: Disable the JTAG interface of the
HPS connector into the JTAG
chain
25
Description
Figure 2-12
is the block diagram of the
Default
1
0
1
0
www.terasic.com
February 17,
2024
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