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Terasic DE10-Agiles User Manual

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DE10-Agilex
1
www.terasic.com
1.1. Q
User Manual
January 29,
2021

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Summary of Contents for Terasic DE10-Agiles

  • Page 1 DE10-Agilex www.terasic.com 1.1. Q User Manual January 29, 2021...

  • Page 2: Table Of Contents

    Configuration ..................13 Status and Setup Components ............16 General User Input/Output ..............22 Clock Circuit ..................26 DDR4 SO-DIMM ................. 29 QSPF-DD Ports ................... 52 PCI Express ..................58 System Status Interface ..............63 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 3 Configure Si5340A in RTL ..............89 Clock_Controller demo for Si5340 ............96 Nios II control for SI5340/ Temperature/ Power/Fan ......98 Board Information IP ................. 103 Chapter 6 Memory Reference Design ..........108 DDR4 SDRAM Test ................108 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 4 PCI Express Library API ..............155 PCIe Reference Design - Fundamental ..........155 PCIe Reference Design - DDR4 ............162 Chapter 9 Transceiver Verification ............172 Transceiver Test Code ..............172 Loopback Fixture ................172 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 5 Serial Lite IV IP Example ..............182 Chapter 10 Dashboard GUI ..............193 10.1 Driver Installed on Host ..............194 10.2 Run Dashboard GUI ................196 Chapter 11 Additional Information ............208 11.1 Getting Help ..................208 DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 6: Chapter 1 Overview

    General Description Targeting the compute and acceleration needs from the edge to the core to the cloud, Terasic’s DE10-Agilex accelerator is purpose-designed to meet the ever-increasing demands for acceleration, compute, and fast data movement. The DE10-Agilex is based on the powerful Intel® Agilex™ FPGA to obtain speed and power breakthrough, with 40% higher performance, 40% lower power for equivalent performance.
  • Page 7 50MHz, 100Mhz and 125MHz Oscillators  Programming PLL providing clock for QSFP-DD interface  Dual clocks oscillators for DDR4 SDRAM SO-DIMM  U.FL connector for external differential clock input  One 2x5 GPIO timing expansion header DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 8: 1.3. Block Diagram

    DE10-Agilex board. To provide maximum flexibility for the users, all key components are connected to the Agilex™ FPGA device. Thus, users can configure the FPGA to implement any system design. DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 9: 1.4. Board Power On

    ATX power provided in the kit to connect to the 8-pin 12V ATX power connector (See Figure 1-2) of the DE10-Agilex board. To power up the board, user need to turn the power switch SW2 to “ON” position. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 10 When the DE10-Agilex is installed on the Host via PCIe slot. Although the Host can provide power to DE10-Agilex board via PCIe slot, but Terasic strongly recommends that users connect an external power (through the 2x4 ATX power connector) to the board.

  • Page 11: 1.5. Board Protection

    In addition, the efficiency of the DE10-Agilex cooling system will decrease with the aging of dust and fans, so customers should re-evaluate the cooling efficiency regularly. DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 12: Chapter 2 Board Component

    It depicts the layout of the board and indicates the location of the connectors and key components. Users can refer to this figure for relative location of the connectors and key components. Figure 2-1 FPGA Board (Top) DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 13: Configuration

    To switch these methods on the DE10-Agilex board, the user needs to switch the MSEL[2:0] pin of FPGA on SW6 and SW7 to change the configuration methods (See Figure 2-3 ). For details, please refer to Setup Configure Mode part of the section 2.3. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 14 16 mode). To set DE10-Agilex board to Avalon-ST mode, users need to set MSEL[2:0] to "101" (See Setup Configure Mode part of the section 2.3). For how to program the configuration file into the Flash, please refer to chapter 4. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 15 D10-Agilex board for AS mode boot. When the Agilex FPGA is running in AS mode, the SDM (Secure device manager) block in the FPGA will actively go to the serial flash to read the stored configuration file to boot the FPGA. To use AS mode, the MSEL[2:0] DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 16: Status And Setup Components

    Status and Setup Components  Status LED The FPGA Board development board includes board-specific status LEDs to indicate board status. Please refer to Figure 2-6 Table 2-1 for the description of the LED indicator. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 17 Illuminates when the FPGA is successfully MAX_CONF_DONE configured. Illuminates when the MAX 10 FPGA System MAX_LOAD Controller is actively configuring the FPGA. Illuminates when the MAX 10 FPGA System MAX_ERROR DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 18 The PCI Express Control DIP switch (SW8) is provided to enable or disable different configurations of the PCIe Connector. Table 2-2 lists the switch controls and description. Figure 2-7 Position of the PCIe mode switch DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 19 FPGA. As currently only Avalon-ST x16 mode is supported (QSPI flash is not soldered on the board), please set MSEL[2:0] to 101 positions as shown in Figure 2-8. Figure 2-8 Position of slide switches SW6 and SW7 for Configuration Mode DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 20 FPGA. Setting Position FACTORY of SW6 to “1” (down position) specifies the default factory image to be loaded, as shown in Figure 2-10. Setting Position FACTORY of SW6 to “0” (up position) specifies the DE10-Agilex to load a user-defined image. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 21 OSC to provide 166.667Mhz or 300Mhz clock to FPGA. This allows users to have more DDR4 reference clock frequencies options for applications. Figure 2-11 The DDR4 reference clock diagram DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 22: General User Input/Output

    SW5 Position Frequency for DDR4 SO-DIMM OFF(Default) 166.667Mhz 300Mhz General User Input/Output This section describes the user I/O interface of the FPGA. Figure 2-13 shows the position of all these components and interface. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 23 Agilex device. Each push-button provides a high logic level or a low logic level when it is not pressed or pressed, respectively. Table 2-5 lists the board references, signal names and their corresponding Agilex device pin numbers. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 24 Table 2-7 Dip Switch Pin Assignments, Schematic Signal Names, and Functions Board Schematic Agilex Description Reference Signal Name Standard Pin Number High logic level when SW in the 1.2V PIN_H51 UPPER position. 1.2V PIN_F51 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 25 GPIO_CLK0 and GPIO_CLK1 are connected to FPGA dedicated clock input and can be configured as two single-ended clock signals. Table 2-10 shows the mapping of the FPGA pin assignments to the 2x5 GPIO header. DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 26: Clock Circuit

    Bi-direction 1.2V GPIO Clock Circuit The development board includes several oscillator (50/100/125 MHz) and one programmable clock generators. Figure 2-15 shows the default frequencies of on-board all external clocks going to the Agilex FPGA. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 27 One oscillator provides a 125 MHz clock used as configuration clock or used as the clock for transceiver calibration. Besides, there is one 100 MHz clock source to use as the FPGA input clock. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 28 PIN_AR14 QSFP-DD port 166.667 DDR4 reference DDR4A_REFCLK_p LVDS PIN_A10 clock for A port 166.667 DDR4 reference DDR4B_REFCLK_p LVDS PIN_L40 clock for B port 166.667 DDR4 reference DDR4C_REFCLK_p LVDS PIN_DC8 clock for C port DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 29: Ddr4 So-Dimm

    153.6Gbps. The memory clock of each DDR4 SO-DIMM SDRAM can be up to 1333MHz (If plug single rank DDR4 SO-DIMM). Figure 2-16 shows the connections between the DDR4 SDRAM SO-DIMMs and Agilex FPGA. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 30 1.2V POD PIN_U12 DDR4A_DQ3 Data [3] 1.2V POD PIN_V13 DDR4A_DQ4 Data [4] 1.2V POD PIN_T17 DDR4A_DQ5 Data [5] 1.2V POD PIN_V17 DDR4A_DQ6 Data [6] 1.2V POD PIN_T13 DDR4A_DQ7 Data [7] 1.2V POD PIN_U16 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 31 1.2V POD PIN_C26 DDR4A_DQ37 Data [37] 1.2V POD PIN_D27 DDR4A_DQ38 Data [38] 1.2V POD PIN_D31 DDR4A_DQ39 Data [39] 1.2V POD PIN_C30 DDR4A_DQ40 Data [40] 1.2V POD PIN_M27 DDR4A_DQ41 Data [41] 1.2V POD PIN_N26 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 32 PIN_P19 DDR4A_DQ69 Data [69] 1.2V POD PIN_M19 DDR4A_DQ70 Data [70] 1.2V POD PIN_L24 DDR4A_DQ71 Data [71] 1.2V POD PIN_N24 DIFFERENTIAL 1.2V DDR4A_DQS0 Data Strobe p[0] PIN_T15 DIFFERENTIAL 1.2V DDR4A_DQS_n0 Data Strobe n[0] PIN_V15 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 33 DDR4A_DQS_n7 Data Strobe n[7] PIN_W22 DIFFERENTIAL 1.2V DDR4A_DQS8 Data Strobe p[8] PIN_L22 DIFFERENTIAL 1.2V DDR4A_DQS_n8 Data Strobe n[8] PIN_N22 Data Bus Inversion DDR4A_DBI_n0 1.2V POD PIN_U14 DDR4A_DBI_n1 Data Bus Inversion 1.2V POD PIN_M7 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 34 PIN_G12 DDR4A_A11 Address [11] SSTL-12 PIN_J12 DDR4A_A12 Address [12] SSTL-12 PIN_D9 DDR4A_A13 Address [13] SSTL-12 PIN_A8 Address [14]/ SSTL-12 DDR4A_A14 PIN_C8 WE_n Address [15]/ DDR4A_A15 SSTL-12 PIN_B7 CAS_n DDR4A_A16 Address [16]/ SSTL-12 PIN_D7 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 35 PIN_C16 Command Input DDR4A_RESET_n Chip Reset 1.2 V PIN_D17 Chip Temperature DDR4A_EVENT_n 1.2 V PIN_F29 Event Chip I2C Serial DDR4A_SDA 1.2 V PIN_J28 Data Bus Chip I2C Serial DDR4A_SCL 1.2 V PIN_G30 Clock DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 36 1.2V POD PIN_A40 DDR4B_DQ18 Data [18] 1.2V POD PIN_B45 DDR4B_DQ19 Data [19] 1.2V POD PIN_C44 DDR4B_DQ20 Data [20] 1.2V POD PIN_D45 DDR4B_DQ21 Data [21] 1.2V POD PIN_C40 DDR4B_DQ22 Data [22] 1.2V POD PIN_A44 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 37 1.2V POD PIN_P59 DDR4B_DQ52 Data [52] 1.2V POD PIN_N54 DDR4B_DQ53 Data [53] 1.2V POD PIN_M55 DDR4B_DQ54 Data [54] 1.2V POD PIN_N58 DDR4B_DQ55 Data [55] 1.2V POD PIN_M59 DDR4B_DQ56 Data [56] 1.2V POD PIN_W58 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 38 DDR4B_DQS_n2 Data Strobe n[2] PIN_C42 DIFFERENTIAL 1.2V DDR4B_DQS3 Data Strobe p[3] PIN_B35 DIFFERENTIAL 1.2V DDR4B_DQS_n3 Data Strobe n[3] PIN_D35 DIFFERENTIAL 1.2V DDR4B_DQS4 Data Strobe p[4] PIN_A56 DDR4B_DQS_n4 Data Strobe n[4] DIFFERENTIAL 1.2V PIN_C56 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 39 Data Bus Inversion 1.2V POD DDR4B_DBI_n4 PIN_B57 Data Bus Inversion 1.2V POD DDR4B_DBI_n5 PIN_U50 Data Bus Inversion 1.2V POD DDR4B_DBI_n6 PIN_M57 Data Bus Inversion 1.2V POD DDR4B_DBI_n7 PIN_T57 Data Bus Inversion 1.2V POD DDR4B_DBI_n8 PIN_L50 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 40 Clock p PIN_M37 SSTL DIFFERENTIAL 1.2V DDR4B_CK_n0 Clock n PIN_P37 SSTL DDR4B_CK1 Clock p SSTL-12 PIN_T45 DDR4B_CK_n1 Clock n SSTL-12 PIN_V45 DDR4B_CKE0 Clock Enable pin SSTL-12 PIN_L36 DDR4B_CKE1 Clock Enable pin SSTL-12 PIN_N36 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 41 Schematic Description I/O Standard Agilex Pin Number Signal Name DDR4C_DQ0 Data [0] 1.2V POD PIN_CH25 DDR4C_DQ1 Data [1] 1.2V POD PIN_CF29 DDR4C_DQ2 Data [2] 1.2V POD PIN_CG24 DDR4C_DQ3 Data [3] 1.2V POD PIN_CH29 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 42 1.2V POD PIN_CF11 DDR4C_DQ33 Data [33] 1.2V POD PIN_CE14 DDR4C_DQ34 Data [34] 1.2V POD PIN_CG14 DDR4C_DQ35 Data [35] 1.2V POD PIN_CF15 DDR4C_DQ36 Data [36] 1.2V POD PIN_CE10 DDR4C_DQ37 Data [37] 1.2V POD PIN_CG10 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 43 1.2V POD PIN_CY25 DDR4C_DQ67 Data [67] 1.2V POD PIN_DC24 DDR4C_DQ68 Data [68] 1.2V POD PIN_DA24 DDR4C_DQ69 Data [69] 1.2V POD PIN_CY29 DDR4C_DQ70 Data [70] 1.2V POD PIN_DC28 DDR4C_DQ71 Data [71] 1.2V POD PIN_DB25 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 44 DDR4C_DQS_n6 Data Strobe n[6] PIN_CE6 DIFFERENTIAL 1.2V DDR4C_DQS7 Data Strobe p[7] PIN_CN6 DIFFERENTIAL 1.2V DDR4C_DQS_n7 Data Strobe n[7] PIN_CL6 DIFFERENTIAL 1.2V DDR4C_DQS8 Data Strobe p[8] PIN_DB27 DDR4C_DQS_n8 Data Strobe n[8] DIFFERENTIAL 1.2V PIN_CY27 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 45 Address [8] SSTL-12 PIN_CV11 DDR4C_A9 Address [9] SSTL-12 PIN_CT11 DDR4C_A10 Address [10] SSTL-12 PIN_CU10 DDR4C_A11 Address [11] SSTL-12 PIN_CR10 DDR4C_A12 Address [12] SSTL-12 PIN_CY7 DDR4C_A13 Address [13] SSTL-12 PIN_DC6 DDR4C_A14 Address [14]/ SSTL-12 PIN_DA6 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 46 Command and DDR4C_PAR Address Parity SSTL-12 PIN_DA10 Input Register ALERT_n DDR4C_ALERT_n 1.2 V PIN_DA4 output Activation DDR4C_ACT_n SSTL-12 PIN_DA14 Command Input DDR4C_RESET_n Chip Reset 1.2 V PIN_CY15 Chip Temperature DDR4C_EVENT_n 1.2 V PIN_CR20 Event DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 47 1.2V POD PIN_CL56 DDR4D_DQ14 Data [14] 1.2V POD PIN_CN52 DDR4D_DQ15 Data [15] 1.2V POD PIN_CK53 DDR4D_DQ16 Data [16] 1.2V POD PIN_CH45 DDR4D_DQ17 Data [17] 1.2V POD PIN_CE50 DDR4D_DQ18 Data [18] 1.2V POD PIN_CF49 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 48 1.2V POD PIN_CL50 DDR4D_DQ48 Data [48] 1.2V POD PIN_DA36 DDR4D_DQ49 Data [49] 1.2V POD PIN_DC32 DDR4D_DQ50 Data [50] 1.2V POD PIN_CY31 DDR4D_DQ51 Data [51] 1.2V POD PIN_DB31 DDR4D_DQ52 Data [52] 1.2V POD PIN_CY35 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 49 PIN_CL54 DDR4D_DQS_n1 Data Strobe n[1] DIFFERENTIAL 1.2V PIN_CH47 DDR4D_DQS2 Data Strobe p[2] DIFFERENTIAL 1.2V PIN_CF47 DDR4D_DQS_n2 Data Strobe n[2] DIFFERENTIAL 1.2V PIN_DB47 DDR4D_DQS3 Data Strobe p[3] DDR4D_DQS_n3 Data Strobe n[3] DIFFERENTIAL 1.2V PIN_CY47 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 50 Data Bus Inversion 1.2V POD PIN_CG48 DDR4D_DBI_n2 Data Bus Inversion 1.2V POD PIN_DC48 DDR4D_DBI_n3 Data Bus Inversion 1.2V POD PIN_DB41 DDR4D_DBI_n4 Data Bus Inversion 1.2V POD PIN_CN48 DDR4D_DBI_n5 Data Bus Inversion 1.2V POD PIN_DC34 DDR4D_DBI_n6 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 51 PIN_CL42 DDR4D_BA1 Bank Select [1] SSTL-12 PIN_CM43 Bank Group Select PIN_CK43 DDR4D_BG0 SSTL-12 Bank Group Select PIN_CM31 DDR4D_BG1 SSTL-12 DIFFERENTIAL 1.2V PIN_CM35 DDR4D_CK0 Clock p SSTL DIFFERENTIAL 1.2V PIN_CK35 DDR4D_CK_n0 Clock n SSTL DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 52: Qspf-Dd Ports

    Calibrated pins for DDR4D_RZQ 1.2 V PIN_CM39 OCT block QSPF-DD Ports The DE10-Agilex board can support two standard QSFP-DD (Quad Small Form Factor Pluggable Double Density) optical modules. The QSFP-DD ports on the DE10-Agilex DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 53 High Speed QSFPDDA_TX_p1 PIN_BK1 data of channel 1 Differential I/O Transmitter inverted data High Speed QSFPDDA_TX_n1 PIN_BJ2 of channel 1 Differential I/O Transmitter non-inverted High Speed QSFPDDA_TX_p2 PIN_BG4 data of channel 2 Differential I/O DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 54 Differential I/O Receiver non-inverted data High Speed QSFPDDA_RX_p2 PIN_BG10 of channel 2 Differential I/O Receiver inverted data of High Speed QSFPDDA_RX_n2 PIN_BH11 channel 2 Differential I/O QSFPDDA_RX_p3 Receiver non-inverted data High Speed PIN_BL10 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 55 QSFPDDA_INTERRUPT_n Interrupt 1.2V PIN_CV25 QSFPDDA_MOD_PRS_n Module Present 1.2V PIN_CR26 QSFPDDA_MOD_SEL_n Module Select 1.2V PIN_DB19 QSFPDDA_RST_n Module Reset 1.2V PIN_DA20 QSFPDDA_SCL 2-wire serial interface clock 1.2V PIN_H21 QSFPDDA_SDA 2-wire serial interface data 1.2V PIN_H23 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 56 Differential I/O Transmitter inverted data High Speed QSFPDDB_TX_n6 PIN_AY5 of channel 6 Differential I/O Transmitter non-inverted High Speed QSFPDDB_TX_p7 PIN_BC4 data of channel 7 Differential I/O QSFPDDB_TX_n7 Transmitter inverted data High Speed PIN_BD5 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 57 Receiver non-inverted data High Speed QSFPDDB_RX_p7 PIN_BC10 of channel 7 Differential I/O Receiver inverted data of High Speed QSFPDDB_RX_n7 PIN_BD11 channel 7 Differential I/O QSFP-DD port A QSFPDDB_REFCLK_p LVDS PIN_AT13 transceiver reference clock DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 58: Pci Express

    (SW6) is connected to the PCI Express to allow different configurations to enable x1, x4, x8 or x16 PCIe lane. Table 2-19 summarizes the PCI Express pin assignments of the signal names relative to the Agilex FPGA. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 59 Add-in card transmit bus PIN_BL56 Differential I/O HIGH Speed PCIE_TX_p3 Add-in card transmit bus PIN_BJ52 Differential I/O HIGH Speed PCIE_TX_n3 Add-in card transmit bus PIN_BH53 Differential I/O PCIE_TX_p4 Add-in card transmit bus HIGH Speed PIN_BF55 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 60 PIN_AN52 Differential I/O HIGH Speed PCIE_TX_n11 Add-in card transmit bus PIN_AM53 Differential I/O HIGH Speed PCIE_TX_p12 Add-in card transmit bus PIN_AK55 Differential I/O HIGH Speed PCIE_TX_n12 Add-in card transmit bus PIN_AL56 Differential I/O DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 61 Add-in card receive bus PIN_BF61 Differential I/O HIGH Speed PCIE_RX_n4 Add-in card receive bus PIN_BG62 Differential I/O HIGH Speed PCIE_RX_p5 Add-in card receive bus PIN_BE58 Differential I/O PCIE_RX_n5 Add-in card receive bus HIGH Speed PIN_BD59 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 62 PIN_AL62 Differential I/O HIGH Speed PCIE_RX_p13 Add-in card receive bus PIN_AJ58 Differential I/O HIGH Speed PCIE_RX_n13 Add-in card receive bus PIN_AH59 Differential I/O HIGH Speed PCIE_RX_p14 Add-in card receive bus PIN_AF61 Differential I/O DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 63: System Status Interface

    FPGA increases, the system will automatically increase the fan speed to reduce the temperature. When the temperature of the FPGA continues to exceed the working range (such as a fan failure condition), the FPGA DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 64 Finally, the board status also can be read on the Agilex FPGA side via the SPI interface connected to the System MAX10 FPGA. Terasic had provided a “board information IP” that allow user can place it in the FPGA to read these board status. Please refer to the section 5.4...
  • Page 65 INFO_SPI_MOSI Master output. 1.2V PIN_CV17 INFO_SPI_CS_n Slave Select, Master output. 1.2V PIN_CR18 DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 66: De10-Agilex 2 Www.terasic.com

     Board damaged for wrong pin/bank voltage assignment.  Board malfunction caused by wrong device connections or missing pin counts for connected ends.  Performance dropped because of improper pin assignments DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 67: General Design Flow

    I/O standard for each user-defined I/O pin. Finally, the Quartus Prime programmer must be used to download SOF file to the FPGA board using JTAG interface. Figure 3-1 the general design flow of building a project DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 68: Using System Builder

     Select FPGA This function is used for if there are more FPGA device supported on the DE10-Agilex board in the feature, users can select FPGA P/N in System Builder as shown in Figure DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 69 The project name entered in the circled area as shown in Figure 3-4, will be assigned automatically as the name of the top-level design entry. Figure 3-4 Project Name in the System Builder window DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 70 Quartus project or it would result in compilation error. Hence please do not select them if they are not needed in the design. To use the DDR4 controller, please refer to the DDR4 SDRAM demonstration in Chapter 6. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 71 (see Figure 3-7) So in system builder, users can choose the SO-DIMM type based on the actual DDR4 SO-DIMM module used as shown in Figure 3-8. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 72 As the Quartus project is created, System Builder automatically generates the associated controller according to users’ desired frequency in Verilog which facilitates users’ implementation as no additional control code is required to configure the programmable oscillator. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 73 Figure 3-10. Users can save the current board configuration information into a .cfg file and load it into the System Builder later. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 74 <Project name>.qsf Quartus Prime Setting File <Project name>.sdc Synopsis Design Constraints File for Quartus Prime <Project name>.htm Pin Assignment Document (*) The si5340_controller is a folder which contains the Verilog files for the DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 75 XCVR_REF_125M 4'h7 `define XCVR_REF_100M 4'h8 wire si5340a_config_done; wire si5340a_controller_start; assign si5340a_controller_start = ~BUTTON[0]; // Reconfigure SI5340A DE10AGILEX_SI5340A_CONFIG si5340a_controller( .iCLK(CLK_50_B2C), .iRST_n(1'b1), .iStart(si5340a_controller_start), .iXCVR_REFCLK_0(`XCVR_REF_156M25),//QSFPDDA_REFCLK_p .iXCVR_REFCLK_1(`XCVR_REF_644M53125),//QSFPDDB_REFCLK_p .iXCVR_REFCLK_RSV(1'b0),//QSFPDDRSV_REFCLK_p. 1: output 156.25MHz, 0: disable output .I2C_CLK(SI5340A_I2C_SCL), .I2C_DATA(SI5340A_I2C_SDA), .oPLL_REG_CONFIG_DONE(si5340a_config_done) DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 76 -period "300.000000 MHz" [get_ports DDR4C_REFCLK_p] create_clock -period "300.000000 MHz" [get_ports DDR4D_REFCLK_p] If the dynamic configurations for the Si5340A clock generators are required, users need to modify the code according to users’ desired behavior. DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 77: Cfi-Flash Programming

    In this chapter, we will introduce how to correctly set the FPGA to work in AVSTx16 mode, how to program bit stream files into the CFI Flash, and how to switch the image file to be loaded. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 78 Figure 4-1 Block diagram of the Avalon-ST x 16 mode on the board Note that the DE10-Agilex board ships with the CFI flash device preprogrammed with two FPGA configurations. The two configuration images are called: factory image and user image, respectively. DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 79: Fpga Configure Operation

    Power on the FPGA board or press the MAX_RST button if board is already powered on, When the configuration is completed, the green Configure Done LED will light. If there is an error, the red Configure Error LED will light (See Figure 4-5). DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 80 Figure 4-2 Position of the MSEL[2:0] switch Figure 4-3 Set MSEL[2:0] to ”110” DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 81: Cfi Flash Memory Map

    Figure 4-4 Configuration Image Selection Figure 4-5 Position of the Configuration status LED CFI Flash Memory Map The DE10-Agilex has one 1-Gbit, 16-bit data width, CFI compatible synchronous flash DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 82: Programming Bit Stream File Into Cfi Flash

    CFI Flash on the DE10-Agilex board, so that the design file can be automatically loaded into the FPGA and executed after the board power on. Figure 4-6 shows the standard CFI Flash programming steps. Users first need to DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 83 JTAG interface and program the .pof file into CFI Flash. In order to help users to quickly program the CFI Flash on the board, Terasic provides some batch files so that users can quickly complete the operations for the CFI Flash such as erasing and programming.
  • Page 84 Factory_HW.sof). Similarly, if users want to program into the User image area, rename their .sof file to User_HW.sof and copy it into the "Flash_Restore" folder.  Convert After the user’s own project’s .sof file has been overwritten into the "Flash_Restore" DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 85: Restore Factory Settings

    Execute the batch file program.bat to start flash programming. After restoring the flash, perform the following procedures to test the restored boot code. Power off the FPGA Board. Set FPGA configuration mode as AVSTx16 Mode by setting SW6/7 DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 86: Flash_Factory Example

    2. On the Assignments menu, click Device. 3. In the Device and Pin Options dialog box, select the Configuration category. 4. In the Configuration window, in the Configuration scheme dropdown list, select the DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 87 Avalon-ST bus width. In the DE10-Agilex Project, please select AVST x 16 mode, as shown in Figure 4-8 5. Click OK to confirm and close the Device and Pin Options dialog box. Figure 4-7 Board Information Figure 4-8 Configuration scheme dropdown list DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 88: Flash_User Example

    Table 4-1) when the FPGA board is shipped. The major difference between the Flash_User and Flash_Factory is the LED control code and the lack of access to the system status on the board. DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 89: Peripheral Reference Design

    Si5340A clock generator can output three differential frequencies from 100MHz ~ 644.53125Mhz though I2C interface configuration. This section will show you how to use FPGA RTL IP to configure each Si5340A PLL and generate users desired output frequency to each peripheral DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 90 In the System Builder window, users can select desired frequencies by selecting a desired output frequency in the pull down menu as shown in Figure 5-2. For details about the System Builder, please refer to Chapter 3 : System Builder. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 91 (0: Module Reset, 1: Normal) Start to Configure（positive edge trigger） iStart input iXCVR_REFCLK_0 Setting Si5340A Output Channel iXCVR_REFCLK_1 input Frequency Value iXCVR_REFCLK_RSV Si5340 Configuration status oPLL_REG_CONFIG_DONE output ( 0: Configuration in Progress, 1: Configuration Complete) DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 92 Si5340A Channel Clock Frequency(MHz) Input Setting 4'h0 644.53125 4'h1 4'h2 322.265625 4'h3 312.5 4'h4 4'h5 184.32 4'h6 156.25 4'h7 4'h8 Table 5-3 Si5340A Controller Reference Clock Frequency Setting for Memory XCVR_REFCLK_RSV Si5340A Channel Clock Frequency(MHz) DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 93 Silicon Labs. This tool can help users to set the Si5340A’s output frequency of each channel through the GUI interface, and it will automatically calculate the Register parameters required for each frequency. The tool download link: http://url.terasic.com/clockuilder_ro_oftware DE10-Agilex www.terasic.com User Manual...
  • Page 94 Figure 5-3 ClockBuilder Pro Wizard After the installation, select Si5340, and configure the input frequency and output frequency as shown in Figure 5-4. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 95 Figure 5-5 Open Design Report on ClockBuilder Pro Wizard Open Si5340 control IP sub-module “si5340a_i2c_reg_controller.v “ as shown Figure 5-6, refer to Design Report parameter to modify sub-module corresponding register value (See Figure 5-7). Figure 5-6 Sub-Module file "si5340a_i2c_reg_controller.v" DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 96: Clock_Controller Demo For Si5340

    User can select the output frequency through button1. Each time button1 is pressed, the output frequency setting will be changed. After selecting the output frequency, press button0 to let si5340a_controller_ip output DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 97 Figure 5-8 Block Diagram of the Clock_Controller Demonstration  Design Tools  Quartus Prime 20.2 Pro Edition  Demonstration File Locations  Hardware project directory: Clock_Controller  Bitstream used: DE10_Agilex_Clock_Controller.sof  Demo batch file: Clock_Controller\demo_batch\test.bat  Demonstration Setup and Instructions DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 98: Nios Ii Control For Si5340/ Temperature/ Power/Fan

    MAX10 FPGA and controlled by internal logic circuits. All collected status data or control commands will be sent to the SPI slave block so that the Aiglex FPGA can read DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 99 Figure 5-11 to provide an interactive interface. With the menu, users can perform the test for the external programmable PLL and board info sensor. Note, pressing ‘ENTER’ should be followed with the choice number. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 100 In the external PLL programming test, the program will program the PLL first, and subsequently use TERASIC custom Platform Designer CLOCK_COUNTER IP to count the clock count in a specified period to check whether the output frequency as changed as configured.
  • Page 101 After the Nios II program is downloaded and executed successfully, a prompt message will be displayed in nios2-terminal. For the PLL Si5340A test, please input key ‘0’ and input the desired output  frequency for two clock sources, as shown in Figure 5-12. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 102 Figure 5-12 Si5340A Demo  For temperature, power monitor and fan test, please input key ‘1’ and press ‘Enter’ in the nios-terminal, as shown in Figure 5-13. DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 103: Board Information Ip

    5-14, there is an SPI slave IP in the system MAX FPGA will read the value of the board status from these registers and it can be output to SPI master logic via SPI interface. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 104 Figure 5-14 Block diagram of the fan speed control demonstration User can placing a board information IP (BOARD_INFO.v ; SPI master) provided by Terasic in the Agilex FPGA, the board status can be obtained via SPI interface from the system MAX FPGA and output to user logic.
  • Page 105 INFO_SPI_CS_n pin. Serial Clock, SPI master output to salve. SCLK Output Please connect this signal to the INFO_SPI_SCLK pin. Information valid, logic high indicates board Info_Valid Output status updated ready. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 106 Temperature of the E-TILE transceiver in the Temp_ETILE FPGA. The unit of the output value is Celsius Output Temperature of the P-TILE transceiver in the Temp_PTILE FPGA. The unit of the output value is Celsius DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 107 BIT 2:FPGA_CONF_DONE,FPGA Configure success, this bit is 1. bit1:LED_MAX_ERROR, FPGA Configure failed, this bit is 0. bit0:LED_MAX_LOAD, When FPGA is during configuration, this bit is 0. Figure 5-16 Waveform of the board status output DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 108: Memory Reference Design

    DDR4 SDRAM controllers. The controller uses 166.667 MHz as a reference clock. It generates one 1333MHz clock as memory clock from the FPGA to the memory and the controller itself runs at quarter-rate in the FPGA i.e. 166.667 MHz. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 109 2. Setup correct parameters in the dialog of the Agilex FPGA External Memory Interfaces.  Design Tools  Quartus Prime 20.2 Pro Edition  Demonstration Source Code  Project Directory: Demonstration\RTL_DDR4_x4/32GB  Bit Stream: DE10_Agilex_golden_top.sof  Demonstration Batch File Demo Batch File Folder: RTL_DDR4_x4 \32GB\demo_batch DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 110: Ddr4 Sdram Test By Nios Ii

    Nios II processor is used to read and write the SDRAM for hardware verification. The DDR4 SDRAM controller handles the complex aspects of using the DDR4 SDRAM by initializing the memory devices, managing the SDRAM banks, and keeping the DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 111 The system flow is controlled by a Nios II program. First, the Nios II program writes test patterns into the whole 8GB of SDRAM. Then, it calls Nios II system function, alt_dache_flush_all(), to make sure all data has been written to SDRAM. Finally, it DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 112 Make sure the SW5 (DDR4 reference clock switch) is set to OFF position to output 166.667Mhz clock.  Power on the FPGA board.  Use a USB Cable to connect the PC and the FPGA board and install USB Blaster DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 113 6-5. The program will display progressing and result information. Press Button0~Button1 of the FPGA board to start SDRAM verify process, and press Button0 for continued test. Figure 6-3 Progress and Result Information for the DDR4A Test DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 114 Figure 6-4 Progress and Result Information for the DDR4B Test DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 115 Figure 6-5 Progress and Result Information for the DDR4A~DDR4D quick test DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 116: Pci Express Reference Design For Windows

    FPGA System and PC System. The FPGA System is developed based on Agilex Hard IP for PCI Express with Avalon-MM DMA. The application software on the PC side is developed by Terasic based on Intel’s PCIe kernel mode driver.

  • Page 117: Pc Pci Express Software Sdk

    Library implemented single named TERASIC_PCIE_AVMM512.DLL. This file is a 64-bit DLL. When the DLL is exported to the software API, users can easily communicate with the FPGA. The library provides the following functions: DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 118: Pci Express Software Stack

    Figure 7-2 PCI Express Software Stack  Install PCI Express Driver on Windows The PCIe driver is locate in the folder: "CDROM\Demonstrations\PCIe_SW_KIT\Windows\PCIe_Driver" The folder includes the following four files:  Altera_pcie_win_driver.cat  Altera_pcie_win_driver.inf  Altera_pcie_win_driver.sys  WdfCoinstaller01011.dll DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 119 Manager dialog. There will be a PCI Device item in the dialog, as shown in Figure 7-3. Move the mouse cursor to the PCI Device item and right click it to select the Updated Driver Software... items. Figure 7-3 Screenshot of launching Update Driver Software… dialog DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 120 Figure 7-4 Dialog of Browse my computer for the driver software 7. In the Browse for driver software on your computer dialog, click the Browse button to specify the folder where altera_pcie_din_driver.inf is located, as shown in Figure 7-5. Click the Next button. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 121 Figure 7-5 Browse for the driver software on your computer 8. When the Windows Security dialog appears, as shown Figure 7-6, click the Install button. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 122 Figure 7-6 Click Install in the dialog of Windows Security 9. When the driver is installed successfully, the successfully dialog will appear, as shown in Figure 7-7. Click the Close button. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 123 Figure 7-7 Click Close when the installation of the Altera PCI API Driver is complete 10. Once the driver is successfully installed, users can see the Altera PCI API Driver under the device manager window, as shown in Figure 7-8. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 124 Dynamically load TERASIC_PCIE_AVMM512.DLL in C/C++ program. To load the DLL, please refer to the PCIe fundamental example below. Call the SDK API to implement the desired application. Users can easily communicate with the FPGA through the PCIe bus through the DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 125: Pci Express Library Api

    This handle value is used as a parameter for other functions, e.g. PCIE_Read32. Users need to call PCIE_Close to release handle once the handle is no longer used.  PCIE_Close Function: Close a handle associated to the PCIe card. Prototype: DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 126 A buffer to retrieve the 32-bit data. Return Value: Return true if read data is successful; otherwise false is returned.  PCIE_Write32 Function: Write a 32-bit data to the FPGA Board. Prototype: bool PCIE_Write32( PCIE_HANDLE hPCIE, DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 127 PcieBar: Specify the target BAR. PcieAddress: Specify the target address in FPGA. pByte: A buffer to retrieve the 8-bit data. Return Value: Return true if read data is successful; otherwise false is returned. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 128  PCIE_DmaRead Function: Read data from the memory-mapped memory of FPGA board in DMA. Prototype: bool PCIE_DmaRead( PCIE_HANDLE hPCIE, PCIE_LOCAL_ADDRESS LocalAddress, void *pBuffer, uint64_t dwBufSize64 Parameters: hPCIE: A PCIe handle return by PCIE_Open function. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 129 Specify the byte number of data which will be written to FPGA. Return Value: Return true if write data is successful; otherwise false is returned.  PCIE_ConfigRead32 Function: Read PCIe Configuration Table. Read a 32-bit data by given a byte offset. DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 130: Pcie Reference Design - Fundamental

    The demo file is located in the batch folder: CDROM\Demonstrations\PCIe_Fundamental\demo_batch The folder includes following files:  FPGA Configuration File: DE10_Agilex.sof  Download Batch file: test.bat  Windows Application Software folder: windows_app, includes  PCIE_FUNDAMENTAL.exe  TERASIC_PCIE_AVMM512.dll DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 131 3. Install the PCIe driver if necessary. The driver is located in the folder: CDROM\Demonstration\PCIe_SW_KIT\Windows\PCIe_Driver. 4. Restart Windows 5. Make sure that Windows has detected the FPGA Board by checking the Windows Device Manager as shown in Figure 7-10. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 132 Figure 7-10 Screenshot for PCIe Driver 6. Go to windows_app folder, execute PCIE_FUNDMENTAL.exe. A menu will appear as shown in Figure 7-11. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 133 7. Type 0 followed by a ENTER key to select Led Control item, then input 15 (hex 0x0f) will make all LEDs on as shown in Figure 7-12. If input 0 (hex 0x00), all LEDs will be turned off. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 134 Figure 7-12 Screenshot of LED Control 8. Type 1 followed by an ENTER key to select Button Status Read item. The button status will be reported as shown in Figure 7-13. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 135 Figure 7-13 Screenshot of Button Status Report 9. Type 2 followed by an ENTER key to select the DMA Testing item. The DMA test result will be reported as shown in Figure 7-14. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 136 Designer (formerly Qsys), the PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 137 Implement dynamically load for TERAISC_PCIE_AVMM.DLL PCIE.h TERASIC_PCIE_AVMM512.h SDK library file, defines constant and data structure The main program PCIE_FUNDAMENTAL.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 138 The LED control is implemented by calling PCIE_Write32 API, as shown below: The button status query is implemented by calling the PCIE_Read32 API, as shown below: The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below: DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 139: Pcie Reference Design - Ddr4

    6. Restart Windows 7. Make sure that Windows has detected the FPGA Board by checking the Windows Control panel. 8. Go to windows_app folder, execute PCIE_DDR4.exe. A menu will appear as shown Figure 7-16. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 140 9. Type 2 followed by the ENTER key to select the Link Info item. The PCIe link information will be shown as in Figure 7-17. Gen3 link speed and x16 link width are expected. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 141 Figure 7-17 Screenshot of Link Info 10. Type 3 followed by the ENTER key to select DMA On-Chip Memory Test item. The DMA write and read test result will be reported as shown in Figure 7-18. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 142 Figure 7-18 Screenshot of On-Chip Memory DMA Test Result 11. Type 4 followed by the ENTER key to select the DMA DDR4-A SODIMM Memory Test item. The DMA write and read test result will be reported as shown in Figure 7-19. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 143 Figure 7-19 Screenshot of the DDR4-A SOSIMM Memory DMA Test Result 12. Type 5 followed by the ENTER key to select the DMA DDR4-B SODIMM Memory Test item. The DMA write and read test result will be reported as shown in Figure 7-20. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 144 Figure 7-20 Screenshot of the DDR4-B SOSIMM Memory DMA Test Result 13. Type 6 followed by an ENTER key to select DMA DDR4-C SODIMM Memory Test item. The DMA write and read test result will be reported as shown in Figure 7-21. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 145 Figure 7-21 Screenshot of the DDR4-C SOSIMM Memory DMA Test Result 14. Type 7 followed by the ENTER key to select the DMA DDR4-D SODIMM Memory Test item. The DMA write and read test result will be reported as shown in Figure 7-22. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 146 Designer (formerly Qsys), the PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 147 Implement dynamically load for TERAISC_PCIE_AVMM.DLL PCIE.h TERASIC_PCIE_AVMM512.h SDK library file, defines constant and data structure The main program PCIE_DDR4.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 148 The PCI express driver is loaded successfully. The LED control is implemented by calling PCIE_Write32 API, as shown below: The button status query is implemented by calling the PCIE_Read32 API, as shown below: DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 149 The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below: The PCIe link information is implemented by PCIE_ConfigRead32 API, as shown below: DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 150 DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 151: Chapter 8 Pci Express Reference Design For Linux

    FPGA System and PC System. The FPGA System is developed based on Agilex Hard IP for PCI Express with Avalon-MM DMA. The application software on the PC side is developed by Terasic based on Intel’s PCIe kernel mode driver.

  • Page 152: Pc Pci Express Software Sdk

    Express Library implemented single file named terasic_pcie512_qsys.so. This file is a 64-bit library file. With the library exported software API, users can easily communicate with the FPGA. The library provides the following functions: DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 153: Pci Express Software Stack

    To make sure the PCIe driver can meet your kernel of Linux distribution, the driver intel_fpga_pcie_drv.ko should be recompiled before it is used. The PCIe driver project is locate in the folder: "CDROM/Demonstrations/PCIe_SW_KIT/Linux/PCIe_Driver" The folder includes the following files:  intel_fpga_pcie_chr.c DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 154 FPGA is detected by the driver as shown in Figure 8-3.  make  sudo sh load_driver  dmesg | tail -n 15 DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 155: Pci Express Library Api

    API. The details of API are described below sections. PCI Express Library API The API is the same as Windows Library. Please refer to the section PCI Express Library API in this document. PCIe Reference Design - DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 156  Download Batch file: test.sh  Linux Application Software folder : linux_app, includes  PCIE_FUNDAMENTAL  terasic_pcie512_qsys.so  Demonstration Setup 1. Install the FPGA board on your PC as shown in Figure 8-4. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 157 4. Execute "sudo -E sh test.sh" command to configure the FPGA 5. Restart Linux 6. Install PCIe driver. The driver is located in the folder: CDROM/Demonstration/PCIe_SW_KIT/Linux/PCIe_Driver. 7. Type “lspci -nn | grep 1172:09c4” to make sure the Linux has detected the FPGA DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 158 9. Type 0 followed by the ENTER key to select the Led Control item, then input 15 (hex 0x0f) will turn all leds on as shown in Figure 8-6. If input 0 (hex 0x00), all led will be turned off. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 159 Figure 8-7 Screenshot of Button Status Report 11. Type 2 followed by the ENTER key to select the DMA Testing item. The DMA test result will be reported as shown in Figure 8-8. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 160 Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 161 Implement dynamically load for terasic_pcie512_qsys.so library file PCIE.h TERASIC_PCIE_AVMM512.h SDK library file, defines constant and data structure The main program PCIE_FUNDAMENTAL.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design. DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 162: Pcie Reference Design - Ddr4

    The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below: PCIe Reference Design - DDR4 The application reference design shows how to add DDR4 Memory Controllers for DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 163 7. Restart Linux 8. Install PCIe driver. 9. Make sure that Linux has detected the FPGA Board. 10. Go to the linux_app folder, execute PCIE_DDR4. A menu will appear as shown in Figure 8-10. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 164 Figure 8-11 Screenshot of Link Info 12. Type 3 followed by the ENTER key to select DMA On-Chip Memory Test item. The DMA write and read test result will be report as shown in Figure 8-12. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 165 Test item. The DMA write and read test result will be reported as shown in Figure 8-13. Figure 8-13 Screenshot of DDR4-A SOSIMM Memory DAM Test Result 14. Type 5 followed by the ENTER key to select the DMA DDR4-B SODIMM Memory DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 166 15. Type 6 followed by the ENTER key to select the DMA DDR4-C SODIMM Memory Test item. The DMA write and read test result will be reported as shown in Figure 8-15. Figure 8-15 Screenshot of DDR4-C SOSIMM Memory DAM Test Result DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 167 Designer (formerly Qsys), the PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 168 Implement dynamically load for terasic_pcie512_qsys.so library file PCIE.h TERASIC_PCIE_AVMM512.h SDK library file, defines constant and data structure The main program PCIE_DDR4.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 169 The PCI express driver is loaded successfully. The LED control is implemented by calling PCIE_Write32 API, as shown below: The button status query is implemented by calling the PCIE_Read32 API, as shown below: DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 170 The memory-mapped memory read and write test is implemented via PCIE_DmaWrite and the PCIE_DmaRead API, as shown below: The PCIe link information is implemented by PCIE_ConfigRead32 API, as shown below: DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 171 DE10-Agilex www.terasic.com User Manual January 29, 2021...

  • Page 172: Chapter 9 Transceiver Verification

    25G bps with NRZ modulation (Total 200G bps for 8 channels). Loopback Fixture To enable an external loopback of the transceiver channels, QSPF-DD loopback fixtures, as shown in Figure 9-1, are required. Figure 9-1 QSFP-DD Loopback Cable DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 173 The loopback fixture can be obtained from the DE10-Agilex product webpage (200G QSFP-DD Loopback Module). The link of the product webpage is list in below: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=1 42&No=1252&PartNo=6 Figure 9-2 the FPGA board with two QSPF-DD loopback fixtures installed. Figure 9-2 QSPF-DD Transceiver Loopback Test in Progress...
  • Page 174 Figure 9-3 The Transceiver PHY setting Figure 9-4 The Transceiver PHY setting The FPGA transceiver PMA setting used are shown in the table below. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 175 Figure 9-5. To terminate the test, press one of the BUTTON0~1 buttons on the FPGA board. The loopback test will terminate as shown in Figure 9-6. Figure 9-5 QSPF-DD Transceiver Loopback Test in Progress DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 176 QSFPDD ports on the FPGA main board. For external loopback test, a QSFPDD or QSFP28 loopback fixture is required, otherwise only internal loopback test be available. Figure 9-7 shows the block diagram of this demonstration. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 177 Test Scrip File alt_ehipc3_fm_100GE\hardware_test_design\hwtest\main.tcl Quartus Version Quartus Prime 20.2 Pro Edition Figure 9-8 shows the IP setup for the demonstration. Single 100GE with optional RSFEC Core Variant is selected and Enable RSFEC is checked. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 178 DE10-Agilex board, as shown in Figure 9-9. 2. Connect the host PC to the FPGA board using a mini-USB cable. Please make sure the USB-Blaster II driver is installed on the host PC. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 179 Figure 9-10. %cd hwtest %source main.tcl %run_test_ex The loopback test report will be displayed in the Tcl Console, as shown in Figure 9-11 Figure 9-12. Figure 9-9 Setup QSFP28 or QSFPDD loopback fixture DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 180 Figure 9-10 Launch the System Console for Ethernet 100G Demo DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 181 Figure 9-11 Ethernet 100G loopback test report for RX Figure 9-12 Ethernet 100G loopback test report for TX DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 182 .sof file will be time limited. Figure 9-13 Block diagram of CPRI PHY demo  Project Information The Quartus project is located in Demonstration folder. Project information is shown in the table below. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 183 If you don’t have a QSFPDD loopback fixture, only internal loopback can be executed successfully. 1. Insert QSFPDD loopback fixtures into the QSFPDD port on the DE10-Agilex board, as shown in Figure 9-14. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 184 Execute test.bat in the folder to configure FPGA. Figure 9-16 shows the screenshot of configure success. Then, do not close the terminal windows, please keep this window open. Figure 9-15 Run the bath file for demonstration DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 185 4. Open the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console (See Figure 9-17 Figure 9-18). Figure 9-17 Open the System Console DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 186 5. As shown in Figure 9-19, click Load Design and select the .sof file for the design example (chose QSFPDDA_CH0123 folder in this example) in the System Console. Figure 9-19 Setup QSFP28 or QSFPDD loopback fixture) DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 187 Figure 9-20 Setup JTAG Master and Serial Lite IV IP 7. Please refer to the Figure 9-21, choose MAC and PCS tab and follow steps 1~4 to implements various CSR for both the hardened custom PCS core and the MAC soft logic. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 188 This process will take a while, please wait. When the message "PMA calibration done!" appears, Link Status will appear in the middle of the window as shown in Figure 9-22 shown DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 189 Figure 9-22 Link initialization is done 8. Please refer to the Figure 9-23, choose GUI Configuration tab and follow steps 1~4 to set JTAG master for demonstration. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 190 1~6 to implement various CSR for the Demo Management module to configure the traffic generator and checker. Figure 9-25 shows the real-time bandwidth calculation measurement result based on the traffic modules instantiated in the example design. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 191 Figure 9-24 Traffic statistics and bandwidth tab Figure 9-25 Traffic statistics and bandwidth DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 192 10. If users enable the “Continuously calculate effective bandwidth” option as shown in Figure 9-26, it will show the real time bandwidth of this demonstration. Figure 9-26 Real time bandwidth DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 193 FPGA core power and 12V input power. Figure 10-1 shows the block diagram of the DE10-Agilex Dashboard. Note that, the Dashboard GUI software only support windows OS. Figure 10-1 Block Diagram of the DE10-Agilex Dashboard DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 194 Figure 10-2 Connection setup for using dashboard system  Install Driver When connect the DE10-Agilex board to the Host. As shown in Figure 10-3, two USB to UART Com Port device is shown in “Device Manager” of Host. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 195 Figure 10-3 Uninstalled USB to UART device Copy the device driver (System CD\Tool\dashboard_gui\Driver) to the Host and install it, as shown in Figure 10-4. Please note that the COM Port number is different in different Host. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 196 Users can find it from the path: Tool\dashboard_gui\Dashboard.exe in the DE10-Agilex system CD and copy it to the Host. Execute the Dashboard.exe, a window will show as Figure 10-6. It will describe the detail functions as below. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 197 DE10-Agilex board status. Users can press Stop button to stop the status data transmission and display.  Reset Button: Press this button to clear the historical data shown in GUI, and record the data again. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 198 When this status is shown in green on the GUI, it means that the fan is abnormal, such as when the fan speed is different from expected  MAX_CONF_DONE Stands for FPGA configure done status. When this status is shown in green DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 199 The information will be refreshed per 1 second, and displays through diagram and number, as shown in Figure 10-9. Figure 10-10 shows the location of the two temperature sensors of Board and Board2 on the GUI. DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 200 Figure 10-9 Temperature section Figure 10-10 Location of the board’s ambient temperature DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 201 Agilex FPGA. Therefore, there will be two voltage and current value displayed on the GUI (See Figure 10-14). When the power consumption of the FPGA is very low, the current value of one power channel will DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 202 PCB impedance of the two power channels, the current of the two power channels may have a little difference instead of the same current value(See Figure 10-16). Figure 10-12 Select “12V Power” DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 203 Figure 10-13 Select “FPGA Monitor Section” Figure 10-14 Two power channels of the FPGA core power Figure 10-15 One of the core power channel’s current is 0 DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 204 Sampling Speed: It can change interval time that the Dashboard GUI sample the board status. Users can adjust it to 1s/10s/1min/Full Speed (0.1s) to sample the board status, as shown in Figure 10-17 Figure 10-18. Figure 10-17 Sampling Speed section DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 205 Figure 10-19 Options of Sampling Speed  Auto Shutdown Status: This option will report whether the board entered “Auto shutdown status” because the FPGA temperature is too high or the fan DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 206 Log File: Click the Export in the File page to save the board temperature, fan speed and voltage data in .csv format document, as shown in Figure 10-21 Figure 10-22. Figure 10-21 Export the log file DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 207 Figure 10-22 Export the log file in .csv format DE10-Agilex www.terasic.com User Manual January 29, 2021...
  • Page 208 Chapter 11 Additional Information 11.1 Getting Help Here are the addresses where you can get help if you encounter problems:  Terasic Technologies 9F., No.176, Sec.2, Gongdao 5 East Dist, HsinChu City, Taiwan, 30070 Email: support@terasic.com Web: www.terasic.com DE10-Agilex Web: DE10-Agilex.terasic.com ...

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