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DDR4B_REFCLK_p
DDR4C_REFCLK_p
DDR4D_REFCLK_p
*(1): The I/O standard of the UFL_CLKIN clock input from J1 to the FPGA needs to be
1.2V. If the input clock I/O standard from the J1 exceeds 1.2V, it should be divided to
1.2V by using two series resistors (R28 and R29).
of different input clock voltage level, the corresponding resistance value settings for
R13 and R28 are required.
Figure 2-21 U.FL clock input signal level setting
Table 2-14
lists the programming clock generator (Si5397A and for QSFP-DD interface)
control pin, signal names, I/O standard and their corresponding Agilex device pin
numbers.
MA27
User Manual
MHz
33.333
LVDS PIN_AG63
MHz
33.333
LVDS PIN_KU36
MHz
33.333
LVDS PIN_MA44
MHz
Figure 2-21
38
clock for A port
DDR4 reference
clock for B port
DDR4 reference
clock for C port
DDR4 reference
clock for D port
shows that in the case
www.terasic.com
February 17,
2024
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