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As shown in
Figure
board to provide additional FPGA input control. When a position of dip switch is in the
DOWN position or the UPPER position, it provides a low logic level or a high logic level
to the Agilex FPGA, respectively.
Table 2-9
lists the signal names and their corresponding Agilex device pin numbers.
Table 2-9 Push-button (FPGA) Pin Assignments, Schematic Signal Names
Board
Schematic
Reference
Signal Name
SW0.1
SW0
SW0.2
SW1
User-Defined LEDs
As shown in
Figure
HPS fabric) and a 5-pin LED bracket connector. The user-controllable LEDs allow
status and debugging signals to be driven to the LEDs from the designs loaded into the
Agilex device. Each LED is driven directly by the Agilex FPGA. The LED is turned on or
off when the associated pins are driven to a low or high logic level, respectively. A list of
the pin names on the FPGA that are connected to the LEDs is given in
5-pin LED bracket connector is reserved for connecting expanded LEDs.
shows the circuit for the connectors and
the FPGA that are connected to the LEDs.
MA27
User Manual
2-15,there are two positions dip switches (SW0) on the FPGA
Description
High logic level when SW in
the UPPER position.
2-16, the FPGA board consists of 5 user-controllable LEDs(one for
I/O Standard
TTable 2-11
list of the connector pin names on
31
FPGA Pin
Number
1.2 V
PIN_L48
1.2 V
PIN_W48
Table
2-10.
Figure 2-17
www.terasic.com
February 17,
2024
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