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2.12 USB 2.0 OTG PHY
The board provides USB interfaces using the SMSC USB3320 controller. A Microchip
USB3320 device is used to interface to a single Type AB Micro-USB connector. This
device supports UTMI+ Low Pin Interface (ULPI) to communicate to USB 2.0 controller
in HPS. As defined by OTG mode, the PHY can operate in Host or Device modes.
When operating in Host mode, the interface will supply the power to the device through
the Micro-USB interface.
HPS.
Figure 2-30 Connections between the HPS of Apollo Agilex and USB controller
Signal Name
HPS_USB_CLK
HPS_USB_DATA[0]
HPS_USB_DATA[1]
HPS_USB_DATA[2]
HPS_USB_DATA[3]
HPS_USB_DATA[4]
HPS_USB_DATA[5]
HPS_USB_DATA[6]
HPS_USB_DATA[7]
HPS_USB_DIR
HPS_USB_NXT
Figure 2-30
Table 2-25 Pin Assignment of USB OTG PHY
FPGA Pin No.
PIN_BM34
PIN_AE16
PIN_BM26
PIN_CD28
PIN_AB6
PIN_CA27
PIN_AE3
PIN_BV28
PIN_AB1
PIN_BJ33
PIN_AB14
MA27
User Manual
shows the connections of USB PTG PHY to the
Description
60MHz Reference Clock Output
HPS USB_DATA[0]
HPS USB_DATA[1]
HPS USB_DATA[2]
HPS USB_DATA[3]
HPS USB_DATA[4]
HPS USB_DATA[5]
HPS USB_DATA[6]
HPS USB_DATA[7]
Direction of the Data Bus
Throttle the Data
80
I/O Standard
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
www.terasic.com
February 17,
2024
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