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SW6.3
CXL_REFCLK_SEL
2.4
Reset Devices
The board provides 4 reset buttons for different system reset situations (see
2-14). These buttons can reset FPGA, System MAX, HPS and FPGA respectively.
Please refer to the following
MA27
User Manual
ON : The reference clock for to FPGA
(CXL_REFCLK_15A_p/n[1:0]) will be
came from MCIO Connectors.
OFF: The reference clock for to FPGA
(CXL_REFCLK_15A_p/n[1:0]) will be
came from on-board PCIe clock
generator.
Table 2-7
for details.
Figure 2-14 Rest devices of the board
28
ON
Figure
www.terasic.com
February 17,
2024
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