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Figure 2-20 Clock circuit of the FPGA Board
A clock buffer (Si53306) is used to duplicate the 50 MHz TCXO output clock, so there
are two 50MHz clocks fed into different Agilex FPGA banks and one clock for USB
blaster II circuit.
The programming clock generator (Si5397A) with low-jitter clock output which are used
to provide special and high- quality clock signals for high-speed transceivers. Through
I2C serial interface, the clock generator controllers in the Agilex FPGA can be used to
program the Si5397As to generate many frequencies to each QSFP-DD port.
For memory interface, the board provide a 33.333Mhz clock and fan out it to four
different clocks to the Agilex FPGA via clock buffer (Si53306). The four clocks are used
for the reference clock of the four DDR4 SODIMMs.
Two UFL connectors provide two external single-ended clock inputs or one external
differential clock inputs. One oscillator provides a 125 MHz clock used as configuration
MA27
User Manual
36
www.terasic.com
February 17,
2024
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