Terasic Mercury A2700 User Manual page 37

clock or used as the clock for transceiver calibration. Besides, there is one 100 MHz
clock source to use as the FPGA input clock.
Finally, for PCIe application, user can choose the clock output from the on-board PCIe
clock generator (Si52204), or clock from the PCIe golden finger/MCIO connector to
feed to Agilex FPGA as reference clock. For detailed information, please refer to
section 2.3: PCIe Clock Select Switch.
Table 2-13 lists the clock source, signal names, default frequency and their
corresponding Agilex device pin numbers.
Table 2-13 Clock Source, Signal Name, Default Frequency, Pin Assignments and
Schematic
Source
Signal Name
CLK_50_B3B
U36
CLK_50_B3C
Y6 CLK_100_B2B_p
Y7 OSC_CLK_1
J2 UFL_CLKIN
CLK_from_SI5397A_p0
CLK_from_SI5397A_p1
QSFPDDA_REFCLK_p
U69
QSFPDDB_REFCLK_p
QSFPDDRSV_REFCLK_p
U20 CLK_30M72
U62 DDR4A_REFCLK_p
MA27
User Manual
Functions
Default I/O
Frequency Standard
1.2V
50.0 MHz
1.2V
100.0MHz LVDS
125MHz LVDS
User
*(1)
Defined
50.0 MHz LVDS PIN_KC31 User application
50.0 MHz LVDS PIN_J41
156.25
LVDS PIN_HJ68 QSFP-DD A port
MHz
156.25
LVDS PIN_JD74 QSFP-DD B port
MHz
156.25
LVDS PIN_HL74
MHz
30.72MHz 1.2V
33.333 LVDS PIN_AA31 DDR4 reference
37
Agilex Pin
Application
Number
PIN_U51 User application
PIN_N45 User application
PIN_LB60 User application
User-supplied
PIN_KU64 configuration
clock
External Clock
PIN_KU56
Input
User application
Reserved for
QSFP-DD port
PIN_KJ27 Reserved
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February 17,
2024