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Terasic DE0-Nano-SoC Edition Design Manual

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SoC-FPGA Design Guide
DE0-Nano-SoC Edition
LAP – IC – EPFL
Version 1.33
Sahand Kashani
René Beuchat
The latest version of this document (complete with all sources) can always be found in [26].

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Summary of Contents for Terasic DE0-Nano-SoC Edition

  • Page 1 SoC-FPGA Design Guide DE0-Nano-SoC Edition LAP – IC – EPFL Version 1.33 Sahand Kashani René Beuchat The latest version of this document (complete with all sources) can always be found in [26].

  • Page 2: Table Of Contents

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] ABLE OF ONTENTS List of Figures ..............................5 Table of Tables ..............................8 Prerequisites ..............................9 Hardware ..............................9 Software ..............................9 4.2.1 Software Versions Used in this Guide .................... 9 4.2.2 Licenses ............................9 Introduction ..............................
  • Page 3 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 7.3.5.1 On-Chip RAM ..........................19 7.3.5.2 Boot ROM ..........................19 HPS-FPGA Interfaces ..........................19 HPS Address Map ..........................19 7.5.1 HPS Address Spaces ........................19 7.5.2 HPS Peripheral Region Address Map .................... 21 HPS Booting and FPGA Configuration ....................23 7.6.1...
  • Page 4 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Programming the FPGA ........................43 Creating Target sdcard Artifacts ......................44 Using the Cyclone V – FPGA – Nios II – Bare-metal ................. 45 10.1 Project Setup ............................45 10.2 Nios II Programming Theory – Accessing Peripherals ................45 10.3...
  • Page 5 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 13.2.2 Scripting U-Boot ........................... 66 13.2.3 Creating Target sdcard Artifacts ....................67 13.3 Linux Kernel ............................67 13.3.1 Getting & Compiling Linux ......................67 13.3.2 Creating Target sdcard Artifacts ....................68 13.4 Ubuntu Core Root Filesystem ......................68 13.4.1...

  • Page 6: List Of Figures

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] IST OF IGURES Figure 6-1. Terasic DE0-Nano-SoC Board [1] ......................12 Figure 6-2. Block Diagram of the DE0-Nano-SoC Board [1] ................. 13 Figure 6-3. Back [1] .............................. 14 Figure 6-4. Front [1] ............................. 14 Figure 7-1. Altera SoC FPGA Device Block Diagram [2, pp. 1-1] ................15 Figure 7-2.
  • Page 7 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 9-18. DE0-Nano-SoC Wiring ........................42 Figure 9-19. Quartus Prime Programmer......................43 Figure 9-20. FPGA Selection ..........................43 Figure 9-21. JTAG Scan Chain ..........................43 Figure 9-22. Programming the FPGA ........................44 Figure 10-1. Incorrect Nios II Peripheral Access in C ................... 45 Figure 10-2.
  • Page 8 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 13-6. Rootfs post-install configuration script to be used AFTER the first boot (“config_post_install.sh”)....................................72 Figure 13-7. Target sdcard directory ........................72 Figure 13-8. Incorrect DE0-Nano-SoC Boot Messages (from U-Boot) ..............74 Figure 13-9. DE0-Nano-SoC Boot Messages (first boot) ..................79 Figure 13-10.

  • Page 9: Table Of Tables

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] ABLE OF ABLES Table 7-1. Possible HPS and FPGA Power Configurations ..................16 Table 7-2. HPS Address Spaces [2, pp. 1-13] ......................20 Table 7-3. Common Address Space Regions [2, pp. 1-15] ..................20 Table 7-4. HPS Peripheral Region Address Map [2, pp. 1-16] ................22 Table 11-1.

  • Page 10: Prerequisites

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] REREQUISITES 4.1 H ARDWARE We use the Terasic DE0-Nano-SoC board in this guide, but the guide can easily be adapted to be used with any other Cyclone V SoC device. 4.2 S OFTWARE This guide assumes users are running a version of the UBUNTU operating system on their host machines.
  • Page 11 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 03/10/2018 P a g e | 10...

  • Page 12: Introduction

    Translation and compilation for FPGAs. The latest models use a PCIe interface or some other way of parameters passing between the main processor and the FPGA We will introduce and use the Terasic DE0-Nano-SoC board, as well as the ARM DS-5 IDE.

  • Page 13: Terasic De0-Nano-Soc Board

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] DE0-N ERASIC OARD Figure 6-1. Terasic DE0-Nano-SoC Board [1] The DE0-Nano-SoC board has many features that allow users to implement a wide range of designed circuits. We will discuss some noteworthy features in this guide.

  • Page 14: Sensors

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition]  2 HPS Reset Buttons ( HPS_RST_n HPS_WARM_RST_n 6.1.7 Sensors  G-Sensor on HPS 6.1.8 Power  12V DC input 6.1.9 Block Diagram Figure 6-2. Block Diagram of the DE0-Nano-SoC Board [1] 03/10/2018 P a g e...

  • Page 15: Layout

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 6.2 L AYOUT Figure 6-3. Back [1] Figure 6-4. Front [1]  Green for peripherals directly connected to the FPGA  Orange for peripherals directly connected to the HPS  Blue for board control 03/10/2018...

  • Page 16: Cyclone V Overview

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] YCLONE VERVIEW This section describes some features of the Cyclone V family of devices. We do not list all features, but only the ones most important to us. All information below, along with the most complete documentation regarding this family can be found in the Cyclone V Device Handbook [2].
  • Page 17 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] The MPU subsystem can boot from  flash devices connected to the HPS pins, or  from memory available on the FPGA portion of the device (when the FPGA portion is previously configured by an external source).

  • Page 18: Features Of The Hps

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 7.2 F EATURES OF THE Figure 7-2. HPS Block Diagram [2, pp. 1-3] The following list contains the main modules of the HPS:  Masters o MPU subsystem featuring dual ARM Cortex-A9 MPCore processors o General-purpose Direct Memory Access (DMA) controller o Two Ethernet media access controllers (EMACs) o Two USB 2.0 On-The-Go (OTG) controllers...

  • Page 19: System Integration Overview

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] o 64 KB on-chip boot ROM o Two UARTs o Four timers o Two watchdog timers o Three general-purpose I/O (GPIO) interfaces o Two controller area network (CAN) controllers o System manager o Clock manager...

  • Page 20: Interface Peripherals

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 7.3.4 Interface Peripherals 7.3.4.1 GPIO Interfaces The HPS provides three GPIO interfaces and offer the following features:  Supports digital de-bounce  Configurable interrupt mode  Supports up to 71 I/O pins and 14 input-only pins, based on device variant ...
  • Page 21 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Name Description Size MPU subsystem 4 GB L3 interconnect 4 GB SDRAM SDRAM controller subsystem 4 GB Table 7-2. HPS Address Spaces [2, pp. 1-13] The following figure shows the relationships between the different HPS address spaces. The figure is NOT to scale.

  • Page 22: Hps Peripheral Region Address Map

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 7.5.2 HPS Peripheral Region Address Map The following table lists the slave identifier, slave title, base address, and size of each slave in the HPS peripheral region. The Slave Identifier column lists the names used in the HPS register map file provided by Altera (more on this later).
  • Page 23 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] SCANMGR Scan manager registers 0xFFF02000 4 KB Boot ROM 0xFFFD0000 64 KB MPUSCU MPU SCU registers 0xFFFEC000 8 KB MPUL2 MPU L2 cache controller registers 0xFFFEF000 4 KB OCRAM On-chip RAM 0xFFFF0000 64 KB Table 7-4. HPS Peripheral Region Address Map [2, pp. 1-16] The programming model for accessing the HPS peripherals in Table 7-4 is the same as for peripherals created on the FPGA fabric.

  • Page 24: Hps Booting And Fpga Configuration

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Note that HWLIB can only be directly used in a BARE-METAL APPLICATION, as it directly references physical addresses. The library can unfortunately NOT be used directly in a LINUX DEVICE DRIVER, because it uses standard header files that are not available in the kernel. Needless to say that a userspace linux program cannot use the library either, as the linux kernel would terminate a user process that tries to access any of these physical addresses directly.
  • Page 25 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 7-5. Independent FPGA Configuration and HPS Booting [2, pp. A-2] Figure 7-5 shows the scheme where the FPGA configuration and the HPS boot occur independently. The FPGA configuration obtains its image from a non-HPS source (Quartus Prime Programmer), while the HPS boot obtains its configuration image from a non-FPGA fabric source.

  • Page 26: Zooming In On The Hps Boot Process

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 7-7. HPS Boots and Performs FPGA Configuration [2, pp. A-3] Figure 7-7 shows the scheme under which the HPS first boots from one of its non-FPGA fabric boot sources, then software running on the HPS configures the FPGA fabric through the FPGA manager. The software on the HPS obtains the FPGA configuration image from any of its flash memory devices or communication interfaces, such as the SD/MMC memory, or the Ethernet port.

  • Page 27: Preloader

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 7.6.2.1 Preloader The preloader is one of the most important boot stages. It is actually what one would call the boot “source”, as all stages before it are unmodifiable. The preloader can be stored on external flash-based memory, or in the FPGA fabric.

  • Page 28: Using The Cyclonev - General Information

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] V – G SING THE YCLONE ENERAL NFORMATION 8.1 I NTRODUCTION The HPS component is a SOFT component, but it does NOT mean that the HPS is a softcore processor. In fact, the HPS exclusively contains HARD LOGIC. The reason it is considered a softcore component originates from the fact that it enables other soft components to interface with the HPS hard logic.

  • Page 29: Application Over An Operating System (Linux)

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 8.3.2 Application Over an Operating System (Linux) Running code over a linux operating system has several advantages. First of all, the kernel releases CPU1 from reset upon boot, so all processors are available. Furthermore, the kernel initializes and makes most, if not all HPS peripherals available for use by the programmer.
  • Page 30 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 8-1. Project Folder Structure Many steps have to be performed in order to configure the Cyclone V before you can use the HPS.  The HARDWARE design is IDENTICAL whether you want to write bare-metal applications, or linux HPS applications.

  • Page 31: Using The Cyclone V - Hardware

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] V – H SING THE YCLONE ARDWARE The details below give step-by-step instructions to create a full system from scratch. Note that this version of the SoC-FPGA Design Guide is an adaptation from that of another board, the DE1-SoC.

  • Page 32: System Design With Qsys - Hps

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 9-1. Basic Nios II System with on-chip memory and JTAG UART 10. Edit the Nios II processor and set as its Reset and Exception vectors. “onchip_memory2_0.s1” 11. Add a PIO component to the system for the LEDs. The DE0-Nano-SoC has 8 LEDs, but we will only use the 4 lower ones with the Nios II processor, so we will use a 4-bit PIO component.

  • Page 33: Instantiating The Hps Component

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 9.3.1 Instantiating the HPS Component 13. To use the HPS, add an to the system. “Arria V/Cyclone V Hard Processor System” 14. Open the HPS’ parameters and have a look around. There are 4 tabs that control various aspects of the HPS’...

  • Page 34: Configuration

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] examine the details of pin J18, to which is connected. The schematic shows that pin G21 is “HPS_KEY_N” connected to 4 sources:  TRACE_D5  SPIS1_MOSI  CAN1_TX  HPS_GPIO54 This can be seen in Qsys, as shown in Figure 9-5.
  • Page 35 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 9-7. Ethernet MAC configuration 18. Our system will boot from the microSD card slot, so we need to enable the SD/MMC controller.  Configure , as shown in “SDIO pin” “HPS I/O Set 0”...

  • Page 36: Hps Clocks Tab

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 9-11. USB, SPI, and I C peripheral pin configurations 21. In Qsys’ tab: “System Contents”  Export under the name . This is a conduit that contains all the “hps_0.hps_io” “hps_0_io” pins configured in the Peripheral Pins tab. We will connect these to our top-level entity later.
  • Page 37 SoC-FPGA Design Guide [DE0-Nano-SoC Edition]  Mirror Addressing: 1 per chip select: 0  Mode Register 0: o Burst Length: Burst chop 4 or 8 (on the fly) o Read Burst Type: Sequential o DLL precharge power down: DLL off o Memory CAS latency setting: 7 ...

  • Page 38: Interfacing With Fpga Peripherals

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition]  Average delay difference between DQ and DQS: 0 ns  Maximum skew within address and command bus: 0.02 ns  Average delay difference between address and command and CK: 0 ns 23. In Qsys’...

  • Page 39: Generating The Qsys System

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 9-13. Adding Buttons and 7-segment Displays to the Lightweight HPS-to-FPGA Bridge 27. In the main Qsys window, select to get rid of any error “System > Assign Base Addresses” messages regarding memory space overlaps among the different components in the system.

  • Page 40: Instantiating The Qsys System

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 9.5 I NSTANTIATING THE YSTEM You now have a complete Qsys system. The system will be available as an instantiable component in your design files. However, in order for Quartus Prime to see the Qsys system, you will have to add the system’s files to your Quartus Prime project.
  • Page 41 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS, hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX, hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX, hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C0_SDAT, hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C0_SCLK, hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C1_SDAT, hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C1_SCLK, hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N, hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N, hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO, hps_0_io_hps_io_gpio_inst_GPIO53 => HPS_LED, hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N, hps_0_io_hps_io_gpio_inst_GPIO61 =>...

  • Page 42: Hps Ddr3 Pin Assignments

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] HPS_ENET_RX_CLK : in std_logic; HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); HPS_ENET_RX_DV : in std_logic; HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); HPS_ENET_TX_EN : out std_logic; HPS_GSENSOR_INT : inout std_logic; HPS_I2C0_SCLK : inout std_logic; HPS_I2C0_SDAT : inout std_logic;...

  • Page 43: Wiring The De0-Nano-Soc

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 9-17. Correct HPS DDR3 Pin Assignment TCL Script Selection 39. Execute “hps_sdram_p0_pin_assignments.tcl” 40. You can now start the full compilation of your design with the flow. “Start Compilation” At this point, we have finished the hardware design process and can proceed to programming the FPGA.

  • Page 44: Programming The Fpga

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 9.8 P FPGA ROGRAMMING THE 41. Open the Quartus Prime Programmer. Figure 9-19. Quartus Prime Programmer 42. Choose the button on the left of Figure 9-19, then choose , as shown in “Auto Detect” “5CSEMA4”...

  • Page 45: Creating Target Sdcard Artifacts

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 44. Enable the checkbox for device , then press the “Program/Configure” “5CSEMA4U23” “Start” button, as shown in Figure 9-22. Figure 9-22. Programming the FPGA We are now done with the Quartus Prime program, and will no longer need it for the rest of this tutorial.

  • Page 46: Using The Cyclone V - Fpga - Nios Ii - Bare-Metal

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 10 U V – FPGA – N II – B SING THE YCLONE METAL 10.1 P ROJECT ETUP 1. Launch the Nios II SBT IDE by executing the following command. $ eclipse-nios2 2. Choose “File > New > Nios II Application and BSP from Template”...

  • Page 47: Nios Ii Programming Practice

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] The available instructions are listed below, and an example of how to correctly access Nios II peripherals is shown in Figure 10-2.  Reading  IORD_8DIRECT(BASE, OFFSET)  IORD_16DIRECT(BASE, OFFSET)  IORD_32DIRECT(BASE, OFFSET)  Writing ...
  • Page 48 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 10-3. nios.c 6. Right-click on the project, and select “DE0_Nano_SoC_demo_nios” “Build Project” 7. The code is now ready to be run on the FPGA. Right-click on the project, “DE0_Nano_SoC_demo_nios” and select . You should be able to see a strobing light effect on the 4 “Run As >...

  • Page 49: Using The Cylone V - Hps - Arm - General

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 11 U V – HPS – ARM – G SING THE YLONE ENERAL 11.1 P ARTITIONING THE SDCARD The DE0-Nano-SoC needs to boot off of a microSD card, so we need to partition it appropriately before we can write to it.

  • Page 50: Hps Programming Theory

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] * Created from SOPC Builder system 'soc_system' in * file 'hw/quartus/soc_system.sopcinfo'. * This file contains macros for module 'hps_0' and devices * connected to the following master: h2f_lw_axi_master * Do not include this header file and another header file created for a * different module or master group at the same time.
  • Page 51 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Up until this point, the hardware and software design process has been IDENTICAL for both BARE-METAL and LINUX HPS applications. This is where the design process DIVERGES between bare-metal and linux HPS applications. If you want to write a bare-metal application for the HPS, then read section 12. If instead you want to write a linux application for the HPS, then read section 13.

  • Page 52: Using The Cyclone V - Hps - Arm - Bare-Metal

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 12 U V – HPS – ARM – B SING THE YCLONE METAL 12.1 P RELOADER In Figure 7-8, we saw that a bare-metal application can only be launched after the preloader has setup the HPS.

  • Page 53: Creating Target Sdcard Artifacts

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 12-2. Preloader Settings Dialog 3. On the main settings page of Figure 12-2, we will only need to modify 2 parameters for our design. a. Under , disable the checkbox. This is necessary to prevent “spl.boot”...

  • Page 54: Setting Up A New C Project

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 12.2.1 Setting Up a New C Project 7. Create a new C project by going to “File > New > Project > C/C++ > C Project” a. Use as the project name. “DE0_Nano_SoC_demo_hps_baremetal” b. Disable the checkbox.

  • Page 55: Writing A Ds-5 Debug Script

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] will use the DDR3 linker script. Under , set the linker script to “C/C++ Build > Settings > GCC C Linker > Image” “<altera_install_directory>/<version>/embedded/host_tools/mentor/gnu/arm/bar HOSTED . The script emetal/arm-altera-eabi/lib/cycloneV-dk-ram- .ld” “hosted” allows the bare-metal application to use some of the host’s functionality. In this case, we use script to be able to see the output of the function on the host’s...

  • Page 56: Setting Up The Debug Configuration

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] wait # Load our bare-metal program. loadfile "$sdir/Debug/DE0_Nano_SoC_demo_hps_baremetal.axf" # Set a breakpoint at our program's "main()" function. tbreak main # Start running the target. # wait at main(). wait Figure 12-4. debug_setup.ds For a comprehensive list of commands supported by the DS-5 debugger, please refer to [8].

  • Page 57: Bare-Metal Programming

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] information when debugging. To do this, set the combobox to “Add peripheral and set it to the description files from directory” directory, as shown in Figure “DE0_Nano_SoC_demo/hw/quartus/soc_system/synthesis” 12-6. This directory contains a file called which has “soc_system_hps_0_hps.svd”...

  • Page 58: Accessing Fpga Peripherals

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] We are not going to implement any interrupts for the various buttons on the board at this time. Therefore, in order to satisfy the HPS-related goals specified in 8.4, we will need to use an infinite loop and do some polling.

  • Page 59: Using Altera's Hwlib - Prerequisites

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 12.2.4.2.1 Using Altera’s HWLIB - Prerequisites In order to be able to use HWLIB to configure a peripheral, 2 steps need to be performed:  You need to INCLUDE the HPS peripheral’s HWLIB HEADER FILE to your code.

  • Page 60: Gpio

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 12.2.4.2.3 GPIO Figure 12-11 shows how we implement the function. This function uses the “handle_hps_led()” HPS_KEY_N button to toggle HPS_LED Once again, we need to add the HWLIB source file for the GPIO peripheral to our DS-5 project directory. The files we will use are listed below: ...

  • Page 61: Launching The Bare-Metal Code In The Debugger

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 12.2.4.3 Launching the Bare-metal Code in the Debugger 19. Once you have finished writing all the application’s code, right-click on the project, and select “DE0_Nano_SoC_demo_hps_baremetal” “Build Project” 20. Switch to the DS-5 Debug perspective, as shown in Figure 12-12.

  • Page 62: Bare-Metal Debugger Tour

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 12.2.4.4 DS-5 Bare-metal Debugger Tour 12.2.4.4.1 “Registers” View [UNAVAILABLE IN SoC EDS 16.0] DS-5’s greatest feature is its view. “Registers” Recall that we provided the debugger with a PERIPHERAL DESCRIPTION FILE in 12.2.3. This file allows the debugger’s...

  • Page 63: App Console

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] The view also highlights the values that changed when stepping through the code while debugging, which helps you track down invalid peripheral writes, side-effects, … However, there is one downside with the view. With so many details in this view, one would “Registers”...

  • Page 64: Using The Cyclone V - Hps - Arm - Linux

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 13 U V – HPS – ARM – L SING THE YCLONE INUX In Figure 7-8, we saw that there are 3 stages before a linux application can be launched:  Preloader  Bootloader ...

  • Page 65: Creating Target Sdcard Artifacts

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 13-2. Preloader Settings Dialog 3. On the main settings page of Figure 13-2, we will only need to modify 1 parameter for our design. a. Under , enabled the checkbox. This option configures the “spl.boot”...
  • Page 66 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] $ git clone \ git://git.denx.de/u-boot.git \ DE0_Nano_SoC_demo/sw/hps/u-boot 7. Change your current working directory to the U-Boot directory. $ cd DE0_Nano_SoC_demo/sw/hps/u-boot 8. We need to compile U-Boot for an ARM machine, but are compiling on an x86-64 machine, so we must cross-compile the bootloader.

  • Page 67: Scripting U-Boot

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 14. Replace the value of the macro with the following definition. We “CONFIG_EXTRA_ENV_SETTINGS” define the environment variables needed to load a user-defined script called from “u-boot.scr” sdcard 0, partition 1 (FAT32 partition) into memory, and to execute it.

  • Page 68: Creating Target Sdcard Artifacts

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] # save environment to sdcard (not needed, but useful to avoid CRC errors on a new sdcard) saveenv ################################################################################ echo --- Programming FPGA --- # load rbf from FAT partition into memory fatload mmc 0:1 ${fpgadata} socfpga.rbf;...

  • Page 69: Creating Target Sdcard Artifacts

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] $ git clone \ https://github.com/altera-opensource/linux-socfpga.git \ DE0_Nano_SoC_demo/sw/hps/linux/source 22. Change your current working directory to the linux directory. $ cd DE0_Nano_SoC_demo/sw/hps/linux/source 23. We need to compile linux for an ARM machine, but are compiling on an x86-64 machine, so we must cross-compile the kernel.

  • Page 70: Obtaining Ubuntu Core

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] In this guide, we will install Ubuntu Core on our DE0-Nano-SoC. Ubuntu Core is the minimal root filesystem (rootfs) needed to run Ubuntu. It consists of a very basic command-line version of the distribution, and can be customized to eventually ressemble the desktop version of Ubuntu most people are familiar with.
  • Page 71 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] localedef -i en_US -c -f UTF-8 en_US.UTF-8 dpkg-reconfigure locales # Configure the timezone. echo "Europe/Zurich" > "/etc/timezone" dpkg-reconfigure -f noninteractive tzdata # Set the machine’s hostname. echo "DE0-Nano-SoC" > "/etc/hostname" tee "/etc/hosts" >"/dev/null" <<EOF 127.0.0.1 localhost 127.0.1.1...

  • Page 72: Post-Install Configuration Script

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] # Make sure that the script will "exit 0" on success or any other # value on error. # In order to enable or disable this script just change the execution # bits. # By default this script does nothing.

  • Page 73: Creating Target Sdcard Artifacts

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] # Edit the “/etc/apt/sources.list” file to configure the package manager. This # file contains a list of mirrors that the package manager queries. By default, # this file has all fields commented out, so the package manager will not have # access to any mirrors.

  • Page 74: Scripting The Complete Procedure

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 44. Write the preloader to the custom partition. “a2” $ sudo dd \ if=DE0_Nano_SoC_demo/sdcard/a2/preloader-mkpimage.bin \ of=/dev/sdb3 \ bs=64K \ seek=0 45. Write the FPGA file, U-Boot file, U-Boot file, linux file, and linux file to .rbf...

  • Page 75: Testing The Setup

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] positional arguments: sdcard_device path to sdcard device file [ex: "/dev/sdb", "/dev/mmcblk0"] =================================================================================== IT IS RECOMMENDED TO USE THE SCRIPT TO AUTOMATE THE FULL SYSTEM CREATION PIPELINE, AND TO GO  GET A SNACK WHILE YOU WAIT FOR IT TO FINISH 13.7 T...
  • Page 76 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Hit any key to stop autoboot: 56. Overwrite the environment variables stored on the sdcard by executing the following commands on the U-Boot command prompt. $ env default –a $ saveenv 57. Reset the board. The system should now run correctly at this point.
  • Page 77 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] reading socfpga.rbf 4244820 bytes read in 226 ms (17.9 MiB/s) --- Booting Linux --- reading zImage 4018912 bytes read in 213 ms (18 MiB/s) reading socfpga.dtb 30225 bytes read in 6 ms (4.8 MiB/s) Kernel image @ 0x1000000 [ 0x000000 - 0x3d52e0 ]...
  • Page 78 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 0.048018] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. 0.048030] hw-breakpoint: maximum watchpoint size is 4 bytes. 0.082191] SCSI subsystem initialized 0.082448] usbcore: registered new interface driver usbfs 0.082510] usbcore: registered new interface driver hub 0.082569] usbcore: registered new device driver usb...
  • Page 79 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 1.340531] oprofile: using timer interrupt. 1.345836] NET: Registered protocol family 10 1.350940] sit: IPv6 over IPv4 tunneling driver 1.356199] NET: Registered protocol family 17 1.360650] NET: Registered protocol family 15 1.365104] can: controller area network core (rev 20120528 abi 9) 1.371308] NET: Registered protocol family 29...
  • Page 80 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] * Starting Send an event to indicate plymouth is up[ OK ] * Stopping Send an event to indicate plymouth is up[ OK ] * Starting configure network device security[ OK ] * Starting configure network device security[ OK ]...
  • Page 81 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 1024 MiB ALTERA DWMMC: 0 reading u-boot.img reading u-boot.img U-Boot 2016.07-rc1-dirty (Feb 10 2017 - 09:18:05 +0100) CPU:...
  • Page 82 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 0.000000] .bss : 0xc085fe3c - 0xc0882eb4 ( 141 kB) 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 0.000000] Hierarchical RCU implementation. 0.000000] Build-time adjustment of leaf fanout to 32. 0.000000] NR_IRQS:16 nr_irqs:16 16 0.000000] L2C: platform provided aux values permit register corruption.
  • Page 83 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 0.721526] RX Checksum Offload Engine supported (type 2) 0.726994] TX Checksum insertion supported 0.731243] Enable RX Mitigation via HW Watchdog Timer 0.736973] socfpga-dwmac ff702000.ethernet eth0: No MDIO subnode found 0.749050] libphy: stmmac: probed 0.752445] eth0: PHY ID 00221622 at 1 IRQ POLL (stmmac-0:01) active 0.759214] ffb40000.usb supply vusb_d not found, using dummy regulator...
  • Page 84 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] * Starting Populate /dev filesystem[ OK ] * Stopping Populate /dev filesystem[ OK ] * Starting Clean /tmp directory[ OK ] * Starting Populate and link to /run filesystem[ OK ] * Stopping Populate and link to /run filesystem[ OK ]...

  • Page 85: Arm Ds-5

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 13-10. DE0-Nano-SoC Boot Messages (second boot) 59. Finally, once you are logged in, we can call our post-installation configuration script to install the required tools from the package manager. sahand@DE0-Nano-SoC:~$ sudo /config_post_install.sh Now that full system is booted and fully configured, we can move on towards building a linux application ...

  • Page 86: Creating A Remote Debug Connection To The Linux Distribution

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] targetted. The reason we use a restricted subset of the library is due to the fact that the library is not fully usable in a user application, as many physical peripheral addresses are employed. We will only use the library to compute offsets and to use the non-intrusive functions it has available.
  • Page 87 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 65. Modify the serial terminal’s settings to match those shown in Figure 13-14, then press to start “OK” the connection. Figure 13-14. ARM DS-5 Serial Terminal Settings 66. You should see the linux login prompt. Login with the same username and password we defined earlier.

  • Page 88: Create An Ssh Remote Connection

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 13-16. Obtaining the DE0-Nano-SoC's IP Address through ARM DS-5’s Serial Terminal 13.8.2.2 Create an SSH Remote Connection 68. Go to “File > New > Other… > Remote System Explorer > Connection” 69. Choose to create an connection.

  • Page 89: Setting Up The Debug Configuration

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 13-18. New SSH Connection In "Remote Systems" View 13.8.2.3 Setting Up the Debug Configuration 74. Right-click on the project, and go to “DE0_Nano_SoC_demo_linux” “Debug As > Debug Configurations…” 75. Choose to create a new debugger configuration by right-clicking on on the left and “DS-5 Debugger”...

  • Page 90: Linux Programming

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] b. Set the to your user directory. In my case it is “Target download directory” “/home/sahand” c. Set the to your user directory. In my case it is “Target working directory” . You should have something similar to Figure 13-20.
  • Page 91 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] The linux operating system calls these modes USER MODE and KERNEL MODE. Processors remain in user mode when executing harmless code in user applications, whereas they transition to kernel mode when executing potentially dangerous code in the system kernel. Examples of dangerous code are handling an interrupt from a peripheral, copying data from a peripheral’s registers to main memory, …...

  • Page 92: Using Altera's Hwlib - Prerequisites

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 13.8.3.1 Using Altera’s HWLIB - Prerequisites We will use a SUBSET of Altera’s HWLIB in this tutorial. In order to be able to use HWLIB to configure a peripheral, 2 steps need to be performed: ...

  • Page 93: Accessing Hps Peripherals

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 13.8.3.2.2 Accessing HPS Peripherals Now that we have opened the physical memory file, we can memory-map a subset of it into our process’ virtual address space. Figure 13-25 shows how this is done for memory-mapping the HPS’ GPIO peripheral.

  • Page 94: Accessing Fpga Peripherals

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] hps_led_value <<= HPS_LED_PORT_BIT; alt_replbits_word(hps_gpio_data, HPS_LED_MASK, hps_led_value); Figure 13-27. handle_hps_led() function. The key to doing memory-mapped IO in linux is to use HWLIB’s OFFSET-based macros with the virtual address returned by as the base address. Note that HWLIB also has macros with ABSOLUTE addresses for...

  • Page 95: Cleaning Up Before Application Exit

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] void setup_fpga_leds() { // Switch on first LED only alt_write_word(fpga_leds, 0x1); Figure 13-29. setup_fpga_leds() function. void handle_fpga_leds() { uint32_t leds_mask = alt_read_word(fpga_leds); if (leds_mask != (0x01 << (HPS_FPGA_LEDS_DATA_WIDTH - 1))) { // rotate leds leds_mask <<= 1;...

  • Page 96: App Console

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 13-33. Switching to the DS-5 Debug Perspective 82. In the view, click on the entry, then click on “Debug Control” “DE0_Nano_SoC_demo_hps_linux” button, as shown on Figure 13-34. The debugger will start an SSH “Connect to Target”...

  • Page 97: Linux Debugger Restrictions

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] Figure 13-36. DS-5 App Console View 13.8.3.5 DS-5 Linux Debugger Restrictions In 12.2.4.4.1, we saw that the DS-5 BARE-METAL debugger had a view which could show the “Registers” registers of all HPS and FPGA peripherals. This was a very handy tool, as it made it easy to verify if registers were accessed and updated correctly.

  • Page 98: Todo

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 14 TODO  Explain MSEL when reprogramming the FPGA from the HPS.  Talk about what the JTAG to Avalon masters are.  Find out how to automatically program the FPGA when writing a bare-metal HPS application. Use command? “tftp”...

  • Page 99: References

    SoC-FPGA Design Guide [DE0-Nano-SoC Edition] 15 R EFERENCES [1] Terasic Technologies, "Terasic - DE Main Boards - Cyclone - DE0-Nano-SoC Board," [Online]. Available: http://de0-nano-soc.terasic.com. [2] Altera Corporation, "Cyclone V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual," 31 July 2014. [Online]. Available: http://www.altera.com/literature/hb/cyclone-v/cv_5v4.pdf.
  • Page 100 SoC-FPGA Design Guide [DE0-Nano-SoC Edition] [16] Altera Corporation, "Cyclone V Device Datasheet," July 2014. [Online]. Available: http://www.altera.com/literature/hb/cyclone-v/cv_51002.pdf. [17] Altera Corporation, "Cyclone V Device Handbook, Volume 1: Device Interfaces and Integration," 22 July 2014. [Online]. Available: http://www.altera.com/literature/hb/cyclone-v/cv_5v2.pdf. [18] ARM, "DS-5 Altera Edition: Bare-metal Debug and Trace," 21 October 2013. [Online]. Available: http://www.youtube.com/watch?v=u_xKybPhcHI.

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