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FPGA, so that users can monitor the status of the board from the host through the
UART interface. See chapter 8 for details.
Finally, the board status also can be read on the Agilex FPGA side via the SPI interface
connected to the System MAX10 FPGA. Terasic had provided a "board information IP"
that allow user can place it in the FPGA to read these board status.
the pin assignments of the SPI interface on the Agilex FPGA.
Figure 2-33 Block diagram of the system status interface
Table 2-29 Pin Assignments, Schematic Signal Names, and Functions for SPI
Schematic
Signal Name
INFO_SPI_SCLK
INFO_SPI_MISO
INFO_SPI_MOSI
INFO_SPI_CS_n
MA27
User Manual
interface of the board status
Description
Serial Clock, SPI master output to
salve.
Master input.
Master output.
Slave Select, Master output.
84
Table 2-29
Agilex Pin
I/O Standard
Number
PIN_B45
1.2V
1.2V
PIN_H46
1.2V
PIN_J45
1.2V
PIN_D46
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