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Table 2-14 Programmable clock generator control pin, Signal Name, I/O standard,
Programmable
clock
generator
SI5397A_I2C_SCL
SI5397A_I2C_SDA
SI5397A_LOL_A
SI5397A_LOL_B
SI5397A_LOL_C
SI5397A_LOL_D
Si5397A
(U69)
SI5397A_LOS_XAXB
SI5397A_RST_n
SI5397A_OE_n
SI5397A_INTR_n
2.7
DDR4 SDRAM Interface
The development board supports four independent banks of DDR4 SDRAM SO-DIMM
(DDR4 SO-DIMM A/B/C/D). DDR4 SO-DIMM B,C and D socket are used for the EMIF
of the FPGA. The I/O bank where DDR4 SO-DIMM A socket is located can implement
Intel Agilex FPGA EMIF IP with the Intel Agilex FPGA Hard Processor Subsystem
(HPS). If HPS EMIF is not used in a system, the DDR4 SO-DIMM Socket A can be
used for the EMIF of the FPGA.
associated running speed for each DDR4 SO-DIMM socket. The maximum capacity of
MA27
User Manual
Pin Assignments and Descriptions
Schematic
I/O Standard
Signal Name
Agilex
Pin
Number
1.2V
PIN_B51
1.2V
PIN_D48
1.2V
PIN_J43 Loss
1.2V
PIN_D42
1.2V
PIN_B41
1.2V
PIN_H44
1.2V
PIN_D44
1.2V
PIN_J49
1.2V
PIN_D50
1.2V
PIN_U45
Table 2-15
shows the maximum capacity and
39
Description
I2C bus, connected with
Si5397A
Of
Lock_A/B/C/D.
These output pins indicate
when DSPLL A, B, C, D is
outof-lock (low) or locked
(high). They can be left
unconnected when not in
use.
Si5397A loss of XA/XB
signal
Si5397A reset signal
Si5397A output enable
signal
This pin is asserted low
when a change in device
status has occurred. It
should be left unconnected
when not in use.
www.terasic.com
February 17,
2024
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