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there is an PCIe Clock Generator(SI52204) that can generate two sets of 100Mhz
clocks for the MCIO connector and two clocks to the clock buffers(SI53254).The
board has two clock buffers, allowing the user to choose the source of the reference
clock provided to the FPGA transceiver from the on-board PCIe Clock Generator or
MCIO connector/PCIe golden finger. Users can set the clock source of clock buffers
through the PCIe Clock Select Switch (SW6). Finally, if the user does not need to run
MCIO RootPort mode or no need for the on-board PCIe Clock Generator to provide
100MHz clock to the FPGA transceiver. User can turn off the clock output of the PCIe
clock generator through the switch on the SW6.
Figure 2-13
shows the position of SW6 on the board and the switch definition. For
detailed settings of SW6, please refer to
Figure 2-12 Block diagram of the PCIe clock application
MA27
User Manual
Table
2-6.
26
www.terasic.com
February 17,
2024
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