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JTAG Bypass Switch
The JTAG interface switch SW7 is to set whether the JTAG interface of the HPS fabric ,
FPGA, System MAX10 FPGA and PCIe EP edge is connected to the JTAG chain in
the board. As long as the interface controlled by the switch is set to "ON" position, the
interface will be included on the JTAG chain on the board. (See
lists the setting of the SW3.
Note, if the user turns any of the position on SW3 to the "OFF" position, but does not
connect the JTAG device on that interface. The JTAG chain on the board will not be
able to form a closed loop and Quartus will not be able to detect the FPGA device.
MA27
User Manual
Figure 2-11 JTAG Bypass Switch
24
Figure 2-11).Table 2-5
www.terasic.com
February 17,
2024
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