1. Manuals
  2. Brands
  3. Terasic Manuals
  4. Computer Hardware
  5. Apollo Agilex
  6. User manual

Terasic Apollo Agilex User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Apollo Agilex
1
www.terasic.com
1.1. Q
User Manual
July 20, 2022

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Apollo Agilex and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Terasic Apollo Agilex

Summary of Contents for Terasic Apollo Agilex

  • Page 1 Apollo Agilex www.terasic.com 1.1. Q User Manual July 20, 2022...

  • Page 2: Table Of Contents

    Setup and Status Components ............18 General User I/O ................. 22 Micro SD Card Socket ................. 24 FMC Connector ................... 25 FMC+ Connector ................. 37 Clock Circuit ..................50 USB to UART ..................53 Apollo Agilex www.terasic.com User Manual July 20, 2022...
  • Page 3 Install Driver for the Board ..........89 Install the USB Blaster II Driver ............89 Install USB to UART Driver ..............89 Chapter 6 Additional Information ............95 Getting Help ..................95 Apollo Agilex www.terasic.com User Manual July 20, 2022...

  • Page 4: Chapter 1 Overview

    Agilex SOM packs unbeatable performance optimization and provides highest real-time compute/watts for edge AI applications. Apollo Agilex SOM takes advantage of the latest Intel® Agilex® SoC with 1400K logic elements to obtain performance and power breakthrough (with up to 40% lower power than Stratix 10 series).

  • Page 5: Board Layout

    Figure 1-1 Apollo Agilex board with heat sink and fan Board Layout The figures below depict the layout of the board and indicate the location of the connectors and key components. Apollo Agilex www.terasic.com User Manual July 20, 2022...
  • Page 6 Figure 1-2 Apollo Agilex board top Apollo Agilex www.terasic.com User Manual July 20, 2022...

  • Page 7: Key Features

    Figure 1-3 Apollo Agilex board bottom Key Features The following hardware is implemented on the Apollo Agilex board:  FPGA Device  Intel® Agilex® SoC FPGA : AGFB014R24B1E1V/AGFB014R24B2E2V  1,400K logic elements (LEs)  229 Mbits embedded memory(M20K)  96 transceivers (up to 28.3Gbps) ...
  • Page 8  Dashboard System  Input Power Monitor  FPGA and Board Temperature Monitor  Fan Control and Monitor  Auto Fan Speed  Auto Shutdown  Power Source  12V from 2x4 PCIe connector Apollo Agilex www.terasic.com User Manual July 20, 2022...

  • Page 9: Block Diagram

    1.3. Block Diagram Figure 1-4 shows the block diagram of the Apollo Agilex board. To provide maximum flexibility for the users, all key components are connected to the Agilex® SoC FPGA device. Thus, users can configure the FPGA to implement any system design.

  • Page 10: Power Requirement

    1.5. Power Requirement  Stand-alone mode When the Apollo Agilex board is used in stand-alone mode, users can use the 12 V ATX power provided in the kit to connect to the 8-pin 12V ATX power connector Figure 1-6 (See ) of the Apollo Agilex.
  • Page 11  Connect to the based board If user wants use the Apollo Agilex board as the module board and connect it to the carrier board. The carrier board needs to provide at least 12V 15A power to the J10 power connector (See Figure 1-7) of the Apollo Agilex board.

  • Page 12: Connectivity

    Figure 1-7 Power connector for connecting based board 1.6. Connectivity Most of the FPGA I/O on the FMC and FMC+ connectors of the Apollo Agilex board are 1.2V standard (*1). Therefore, if users want to connect FMC/FMC+ daughter cards or other motherboards to the Apollo Agilex board, users need to pay special attention to whether they directly support the 1.2V I/O standard...
  • Page 13 Samtec : ASP-134486-01 FMC+ Samtec : ASP-184330-01 Samtec : ASP-184329-01 Power Connector Samtec : UPT-02-03.0-01-L-V Samtec : UPS-02-07.0-02-L-V Apollo Agilex www.terasic.com User Manual July 20, 2022...

  • Page 14: Chapter 2 Board Component

    Apollo Agilex. Configuration Interface This section describes the configuration mode for Agilex SoC FPGA available on the Apollo Agilex. The peripheral circuits and usage scenarios for each mode will be listed. As shown in Figure 2-1, the mode select pin of the FPGA on the Apollo Agilex board has been set to Active Serial (AS) mode using resistors.
  • Page 15 Figure 2-2 shows the architecture of the AS mode of the Apollo Agilex board. Figure 2-2 AS mode for the Apollo Agilex board For more information on the configuration of Agilex SoC FPGAs, please refer to the file: Intel Agilex Configuration User Guide ...
  • Page 16 FPGA fabric after powering on. More details can be found in the user documentation: Intel® Agilex™ SoC FPGA Boot User Guide. The factory setting of the SoC boot of the Apollo Agilex board is the FPGA Configuration First Mode. The architecture is shown in the Figure 2-3.
  • Page 17 Finally, the OS boots and applications are scheduled for runtime launch.  JTAG Programming The JTAG interface of the Apollo Agilex is mainly implemented by the USB Blaster II circuit on the board. For programming by on-board USB Blaster II, the following...

  • Page 18: Setup And Status Components

    Setup and Status Components This section will introduce the use of the switch for setup on the Apollo Agilex board, as well as a description of the various status LEDs.  Status LED The FPGA development board includes board-specific status LEDs to indicate board status.
  • Page 19 The JTAG interface switch SW3 is to set whether the JTAG interface of the FMC and FMC + connector is connected to the JTAG chain in the Apollo Agilex board. Both the FMC+ and FMC connectors will not be included in the JTAG chain if the switches are set to ON position (See Figure 2-5).Table 2-2...
  • Page 20 OFF: Enable the JTAG interface of the FMC connector into the JTAG chain  FMC_VCCIO Select Header Some of the FPGA pin’s I/O standard connected with the HPC (High Pin Count) part of Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 21 Table 2-3 FPGA I/Os on the FMC connector which can be changed I/O standard to 1.2 or 1.5V FMC Pins which can modify I/O stadnard FMC_HA_p[23..0] FMC_HA_n[23..0] FMC_HB_p[21..0] FMC_HB_p[21..0] FMC_HB_n[21..0] FMC_CLK_M2C_p[1..0] FMC_CLK_M2C_n[1..0] Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 22: General User I/O

    This section describes the user I/O interface of the FPGA and HPS fabric. Please note that the HPS and FPGA portions of the device each have their own pins. Pins are not freely shared between the HPS and the FPGA fabric. Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 23 Agilex SoC device pin numbers. Table 2-7 Dip Switch Pin Assignments, Schematic Signal Names, and Functions Board Schematic FPGA Pin Description Reference Signal Name Standard Number Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 24: Micro Sd Card Socket

    The board supports Micro SD card interface with x4 data lines. It serves for an external storage for the HPS fabric. Figure 2-8 shows signals connected between the HPS and Micro SD card socket. Table 2-10 lists the pin assignment of Micro SD card socket to Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 25: Fmc Connector

    The FMC interfaces support JTAG, clock outputs and inputs, high-speed serial I/O (transceivers), and single-ended or differential signaling. There is one FMC connector on the Apollo Agilex board, it is a High Pin Count (HPC) size of connector, The HPC connector on Apollo Agilex board can provides 169 user-define, single-ended signals (80 pair differential I/O) and 10 serial transceiver pairs.
  • Page 26 Below we will introduce according to the individual functions of FMC connector. Figure 2-9 FMC connector on Apollo Agilex board  Clock Interface Table 2-11 shows the FPGA clock interface pin placement on the FMC connector. Table 2-11 FMC clock input interface distribution...
  • Page 27 (SW3.2) on the Apollo Agilex board. In the board's default setting, the JTAG interface of the FMC connector is bypassed to keep the Apollo Agilex board JTAG chain to maintain close loop. For detailed setting, please refer to Section 2.2: JTAG Interface Switch.
  • Page 28 "E-Tile Transceiver PHY Overview".  Component Information of the FMC Connector For information on the FMC part number used on the Apollo Agilex board and the male connector connected to it, refer to Table 1-1 in the section 1.6. ...
  • Page 29 FMC_HA_p[11] PIN_CH17 FMC HA bank data p11 1.2V or 1.5V *(1) FMC_HA_p[12] PIN_CH27 FMC HA bank data p12 1.2V or 1.5V *(1) FMC_HA_p[13] PIN_CG26 FMC HA bank data p13 1.2V or 1.5V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 30 FMC_HA_n[15] PIN_CE20 FMC HA bank data n15 1.2V or 1.5V *(1) FMC_HA_n[16] PIN_CK17 FMC HA bank data n16 1.2V or 1.5V *(1) FMC_HA_n[17] PIN_CK27 FMC HA bank data n17 1.2V or 1.5V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 31 FMC_HB_p[19] PIN_CU26 FMC HB bank data p19 1.2V or 1.5V *(1) FMC_HB_p[20] PIN_CU22 FMC HB bank data p20 1.2V or 1.5V *(1) FMC_HB_p[21] PIN_CU28 FMC HB bank data p21 1.2V or 1.5V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 32 FMC_LA_p[2] PIN_CV13 FMC LA bank data p2 1.2V FMC_LA_p[3] PIN_DC10 FMC LA bank data p3 1.2V FMC_LA_p[4] PIN_CU6 FMC LA bank data p4 1.2V FMC_LA_p[5] PIN_DB11 FMC LA bank data p5 1.2V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 33 FMC_LA_p[30] PIN_CH11 FMC LA bank data p30 1.2V FMC_LA_p[31] PIN_CM5 FMC LA bank data p31 1.2V FMC_LA_p[32] PIN_CG14 FMC LA bank data p32 1.2V FMC_LA_p[33] PIN_CH7 FMC LA bank data p33 1.2V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 34 FMC_LA_n[24] PIN_CL6 FMC LA bank data n24 1.2V FMC_LA_n[25] PIN_CK3 FMC LA bank data n25 1.2V FMC_LA_n[26] PIN_CE6 FMC LA bank data n26 1.2V FMC_LA_n[27] PIN_CK7 FMC LA bank data n27 1.2V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 35 High Speed FMC_DP_C2M_p[6] PIN_BB1 transceiver Differential I/O Transmit pair p7 of the FPGA High Speed FMC_DP_C2M_p[7] PIN_BC4 transceiver Differential I/O Transmit pair p8 of the FPGA High Speed FMC_DP_C2M_p[8] PIN_BF1 transceiver Differential I/O Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 36 1.2 V  *(1): The FMC_VCCIO value depends on the setting of JP2, which can adjust the FMC_VCCIO to 1.2V or 1.5V. Please refer to section 2.2 : “FMC_VCCIO Select Header” for details. Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 37: Fmc+ Connector

    FPGA pins and the FMC pins.  *(3): FPGA dedicated clock input pin. FMC+ Connector In addition to an FMC connector on the Apollo Agilex board, there is also an FMC + connector for expanding FPGA I/Os (See Figure 2-11). The main difference between...
  • Page 38 Table 2-15 Power Supply of the FMC Supplied Voltage Max. Current Limit 3.3V 1.2V(VADJ)  JTAG Chain on FMC The JTAG chain on the Apollo Agilex board supports JTAG interface extension to the Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 39 (SW3.1) on the Apollo Agilex board. In the board's default setting, the JTAG interface of the FMC connector is bypassed to keep the Apollo Agilex board JTAG chain to maintain close loop. For detailed setting, please refer to Section 2.2: JTAG Interface Switch.
  • Page 40  FPGA Pin Assignments for FMCP Connector Figure 2-14 shows the pin out table of the FMC connector on the Apollo Agilex and Table 2-16 lists the FMC connector pin assignments, signal names and function. Figure 2-14 FMC+ pin out table Apollo-Agilex SoM www.terasic.com...
  • Page 41 FMCP HA bank data p7 1.2 V FMCP_HA_p[8] PIN_CG42 FMCP HA bank data p8 1.2 V FMCP_HA_p[9] PIN_CH41 FMCP HA bank data p9 1.2 V FMCP_HA_p[10] PIN_CG38 FMCP HA bank data p10 1.2 V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 42 FMCP HA bank data n11 1.2 V *(1) PIN_CL38 FMCP HA bank data n12 1.2 V FMCP_HA_n[12] FMCP_HA_n[13] PIN_CK43 FMCP HA bank data n13 1.2 V FMCP_HA_n[14] PIN_CL36 FMCP HA bank data n14 1.2 V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 43 FMCP HB bank data p15 1.2 V FMCP_HB_p[16] PIN_CU40 FMCP HB bank data p16 1.2 V FMCP_HB_p[17] PIN_CV31 FMCP HB bank data p17 1.2 V FMCP_HB_p[18] PIN_CU32 FMCP HB bank data p18 1.2 V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 44 FMCP HB bank data n21 1.2 V *(1) PIN_CG50 FMCP LA bank data p0 1.2 V FMCP_LA_p[0] FMCP_LA_p[1] PIN_CN54 FMCP LA bank data p1 1.2 V FMCP_LA_p[2] PIN_CM45 FMCP LA bank data p2 1.2 V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 45 FMCP LA bank data p27 1.2 V FMCP_LA_p[28] PIN_DB45 FMCP LA bank data p28 1.2 V FMCP_LA_p[29] PIN_CV53 FMCP LA bank data p29 1.2 V FMCP_LA_p[30] PIN_CV47 FMCP LA bank data p30 1.2 V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 46 FMCP LA bank data n21 1.2 V FMCP_LA_n[22] PIN_CY57 FMCP LA bank data n22 1.2 V FMCP_LA_n[23] PIN_DA56 FMCP LA bank data n23 1.2 V FMCP_LA_n[24] PIN_CY47 FMCP LA bank data n24 1.2 V Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 47 High Speed FMCP_DP_C2M_p[4] FPGA transceiver Differential I/O PIN_BE52 Transmit pair p5 of the High Speed FMCP_DP_C2M_p[5] FPGA transceiver Differential I/O PIN_BB55 Transmit pair p6 of the High Speed FMCP_DP_C2M_p[6] FPGA transceiver Differential I/O Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 48 High Speed FMCP_DP_M2C_p[4] FPGA transceiver Differential I/O PIN_BE58 Receiver pair p5 of the High Speed FMCP_DP_M2C_p[5] FPGA transceiver Differential I/O PIN_BB61 Receiver pair p6 of the High Speed FMCP_DP_M2C_p[6] FPGA transceiver Differential I/O Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 49 FMCP_GA[0] 3.3 V address 0 PIN_CN48 FMCP geographical *(2) FMCP_GA[1] 3.3 V address 1 PIN_CL52 Management serial clock *(2) FMCP_SCL 3.3 V line PIN_CU56 Management serial data *(2) FMCP_SDA 3.3 V line Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 50: Clock Circuit

    The development board includes a 50 MHz TCXO, a 125 MHz OSC, a 100Mhz OSC and two programmable clock generators. Figure 2-15 shows the default frequencies of on-board all external clocks going to the Agilex SoC FPGA. Figure 2-15 Clock circuit of the FPGA Board Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 51 Besides, there is one 100 MHz clock source to use as the FPGA input clock. Finally, the Apollo Agilex board has reserved a high stability OCXO oscillator (U45, not installed), which is reserved for use when users need CRPI applications.
  • Page 52 DIFFERENTIAL port QSFP28_REFCLK_p 156.25MHz PIN_AJ12 LVPECL reference clock port Reserved DIFFERENTIAL clock for QSFP28RSV_REFCLK_p 184.32MHz PIN_AR14 LVPECL QSFP28 port High Reserved for PIN_CN8 Stability CLK_30M72 30.72MHz 1.2V CPRI (Reserved) OCXO(Not application installed) Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 53: Usb To Uart

    MAX10 device. It allows users to monitor various status of the board such as temperature and voltage value from the Host. The Apollo Agilex uses a USB hub to allow three USB to UART interface (HPS fabric, FPGA and system MAX10) and USB Blaster II circuit to share a Mini USB connector to connect to the host.
  • Page 54 1.2V  USB to UART for FPGA The Apollo Agilex board is also equipped with a UART interface for FPGA (with hardware flow control: CTS/RTS), allowing users to communicate with the FPGA and the Host through UART. This UART interface is converted to USB interface via a dual UART to USB (CP2105).

  • Page 55: Ddr4 Sodimm Socket

    (such as a fan failure condition), the FPGA power will be cut to protect the board. See chapter 3 for details. Terasic also provide a “board information IP” that allow user can place it in the Agilex FPGA to read these board status. Please refer to the section 2.5 of the Apollo Agilex demonstration manual.
  • Page 56 Table 2-20 Pin Assignment of UART Interface DDR4 SO-DIMM Socket A DDR4 SO-DIMM Socket B (HPA Fabric and FPGA) (FPGA) Support Rank Single Support ECC Speed for B2E2 device 2666MT/s Speed for B1E1 device 3200MT/s Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 57 1.2-V POD PIN_A12 DDR4A_DQ21 Data [21] 1.2-V POD PIN_C12 DDR4A_DQ22 Data [22] 1.2-V POD PIN_D17 DDR4A_DQ23 Data [23] 1.2-V POD PIN_C16 DDR4A_DQ24 Data [24] 1.2-V POD PIN_F17 DDR4A_DQ25 Data [25] 1.2-V POD PIN_F13 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 58 1.2-V POD PIN_U26 DDR4A_DQ56 Data [56] 1.2-V POD PIN_L30 DDR4A_DQ57 Data [57] 1.2-V POD PIN_L26 DDR4A_DQ58 Data [58] 1.2-V POD PIN_N26 DDR4A_DQ59 Data [59] 1.2-V POD PIN_P27 DDR4A_DQ60 Data [60] 1.2-V POD PIN_M27 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 59 DDR4A_DQS_n3 Data Strobe n[3] DIFFERENTIAL 1.2-V PIN_L22 DDR4A_DQS4 Data Strobe p[4] DIFFERENTIAL 1.2-V PIN_N22 DDR4A_DQS_n4 Data Strobe n[4] DIFFERENTIAL 1.2-V PIN_U22 DDR4A_DQS5 Data Strobe p[5] DIFFERENTIAL 1.2-V PIN_W22 DDR4A_DQS_n5 Data Strobe n[5] Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 60 PIN_T7 DDR4A_DBI_n8 DDR4A_A0 Address [0] SSTL-12 PIN_T17 DDR4A_A1 Address [1] SSTL-12 PIN_V17 DDR4A_A2 Address [2] SSTL-12 PIN_U16 DDR4A_A3 Address [3] SSTL-12 PIN_W16 DDR4A_A4 Address [4] SSTL-12 PIN_T15 DDR4A_A5 Address [5] SSTL-12 PIN_V15 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 61 On Die DDR4A_ODT SSTL-12 PIN_M15 Termination DDR4A_CS_n Chip Select SSTL-12 PIN_L16 Command and DDR4A_PAR Address Parity SSTL-12 PIN_N12 Input Register ALERT_n DDR4A_ALERT_n 1.2 V PIN_L6 output Activation DDR4A_ACT_n SSTL-12 PIN_N16 Command Input Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 62 1.2-V POD PIN_J40 DDR4B_DQ13 Data [13] 1.2-V POD PIN_F45 DDR4B_DQ14 Data [14] 1.2-V POD PIN_F41 DDR4B_DQ15 Data [15] 1.2-V POD PIN_J44 DDR4B_DQ16 Data [16] 1.2-V POD PIN_B41 DDR4B_DQ17 Data [17] 1.2-V POD PIN_A40 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 63 1.2-V POD PIN_D47 DDR4B_DQ48 Data [48] 1.2-V POD PIN_A54 DDR4B_DQ49 Data [49] 1.2-V POD PIN_B55 DDR4B_DQ50 Data [50] 1.2-V POD PIN_D59 DDR4B_DQ51 Data [51] 1.2-V POD PIN_F61 DDR4B_DQ52 Data [52] 1.2-V POD PIN_C54 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 64 Data Strobe n[1] PIN_J42 DIFFERENTIAL 1.2-V DDR4B_DQS2 Data Strobe p[2] PIN_A42 DIFFERENTIAL 1.2-V DDR4B_DQS_n2 Data Strobe n[2] PIN_C42 DIFFERENTIAL 1.2-V DDR4B_DQS3 Data Strobe p[3] PIN_B35 DIFFERENTIAL 1.2-V DDR4B_DQS_n3 Data Strobe n[3] PIN_D35 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 65 DDR4B_DBI_n3 1.2-V POD PIN_A36 Data Bus Inversion DDR4B_DBI_n4 1.2-V POD PIN_G50 Data Bus Inversion DDR4B_DBI_n5 1.2-V POD PIN_A50 Data Bus Inversion DDR4B_DBI_n6 1.2-V POD PIN_B57 Data Bus Inversion DDR4B_DBI_n7 1.2-V POD PIN_F57 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 66 Bank Group Select DDR4B_BG1 SSTL-12 PIN_M33 DIFFERENTIAL 1.2-V DDR4B_CK Clock p PIN_M37 SSTL DIFFERENTIAL 1.2-V DDR4B_CK_n Clock n PIN_P37 SSTL DDR4B_CKE Clock Enable pin SSTL-12 PIN_L36 On Die DDR4B_ODT SSTL-12 PIN_M35 Termination Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 67: Usb 2.0 Otg Phy

    HPS. As defined by OTG mode, the PHY can operate in Host or Device modes. When operating in Host mode, the interface will supply the power to the device through the Micro-USB interface. Figure 2-21 shows the connections of USB PTG PHY to the HPS. Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 68: Gigabit Ethernet

    Figure 2-21 Connections between the HPS of Apollo Agilex and USB controller Table 2-23 Pin Assignment of USB OTG PHY Signal Name FPGA Pin No. Description I/O Standard 1.8V HPS_USB_CLK PIN_AH5 60MHz Reference Clock Output HPS_USB_DATA[0] PIN_AB1 HPS USB_DATA[0] 1.8V PIN_AG4 1.8V...
  • Page 69 Figure 2-22 Connections between the HPS of Apollo Agilex and RGMII MAC There are two LEDs, a green LED (LEDG) and a yellow LED (LEDY), which represent the status of the Ethernet PHY (KSZ9031RN). The LED control signals are connected to the LEDs on the RJ45 connector.

  • Page 70: 2X6 Gpio Header

    HPS_ENET_TX_CLK PIN_AC4 GMII Transmit Clock 2.12 2x6 GPIO Header The Apollo Agilex board provides two 2x6 pin GPIO headers (HPS and FPGA for each) to expand the I/O of Agilex SoC FPGA (See Figure 2-24). Each header has numbers of the digital FPGA I/O user pins connected to the Agilex SoC FPGA, two 3.3V power pins and two ground pins.
  • Page 71 FPGA 2x6 header GPIO2 GPIO_D[3] PIN_N48 FPGA 2x6 header GPIO3 1.2V GPIO_D[4] PIN_M49 1.2V FPGA 2x6 header GPIO4 GPIO_D[5] PIN_P49 1.2V FPGA 2x6 header GPIO5 GPIO_D[6] PIN_L50 1.2V FPGA 2x6 header GPIO6 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 72: Qsfp28 Port

    Table 2-27 QSFP28 Pin Assignments, Schematic Signal Names, and Functions Stratix 10 Schematic Description I/O Standard GX/SX Pin Signal Name Number HSSI QSFP28_TX_P0 Transmitter data of channel 0 DIFFERENTIAL PIN_BP1 HSSI QSFP28_TX_N0 Transmitter data of channel 0 DIFFERENTIAL PIN_BN2 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 73 Receiver data of channel 2 DIFFERENTIAL PIN_BV7 HSSI QSFP28_RX_N2 Receiver data of channel 2 DIFFERENTIAL PIN_BU8 HSSI QSFP28_TX_P3 Transmitter data of channel 3 DIFFERENTIAL PIN_BW4 HSSI QSFP28_TX_N3 Transmitter data of channel 3 DIFFERENTIAL PIN_BY5 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 74 2-wire serial interface clock 3.0-V LVTTL PIN_H19 QSFP28_SDA 2-wire serial interface data 3.0-V LVTTL PIN_J22 QSFP28_LP_MODE Low Power Mode 3.0-V LVTTL PIN_G20 QSFP28_INTERRUPT_ Interrupt 3.0-V LVTTL PIN_H21 QSFP28_MOD_PRS_n Module Present 3.0-V LVTTL PIN_F21 Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 75: Chapter 3 Dashboard Gui

    To use the dashboard system, users need to install the USB to UART driver on the host first, so that user can establish a connection with the Apollo Agilex board. This section will describe how to install USB to UART driver on the windows OS host.

  • Page 76: Run Dashboard Gui

    Connect the USB Mini USB connector of the Apollo Agilex board to the host PC USB port through mini USB cable. Connect power to the Apollo Agilex board. Power on the Apollo Agilex board. Figure 3-2 Connection setup for using dashboard system ...
  • Page 77 3-4, there is a Start button at the bottom-left of the GUI window. Click it to run the program (Start will change to Stop), it will show the Apollo Agilex board status. Users can press Stop button to stop the status data transmission and display.
  • Page 78 3-5, once you press the “Start” button, it CONF_DONE :As shown in Figure will show the status LED number on the Apollo Agilex board. For these LEDs Note that “CONF_DONE” stands for function, please refer to section 2.2. FPGA configure done status. There is no LED on Apollo Agilex board to display FPGA configure status.
  • Page 79  FPGA/Board/Transceivers(E-title and P-tile) Temperature: The Dashboard GUI will real-time show the fan speed, Apollo Agilex board ambient and FPGA temperature. Users can know the board temperature in time. The information will be refreshed per 1 second, and displays through diagram and number, as shown Figure 3-6.
  • Page 80 Figure 3-6 Temperature section  Fan RPM: It displays the real-time speed of the fan on the Apollo Agilex board, as shown in Figure 3-7. Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 81 Figure 3-7 FAN RPM section  12V Power monitor: It displays the real-time 12V Power voltage and consumption current on the Apollo Agilex board, as shown in Figure 3-8. Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 82 Sampling Speed: It can change interval time that the Dashboard GUI sample the board status. Users can adjust it to 1s/10s/1min/Full Speed (0.1s) to sample the board status, as shown in Figure 3-9 Figure 3-10. Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 83  Board Information: There is a File page on the upper left of the Dashboard GUI program window, click the Board Information to get the current software version and the Apollo Agilex board version, as shown in Figure 3-11. Note, user needs to stop the system monitor (press the “Stop”...
  • Page 84 Export in the File page to save the board temperature, fan speed and voltage data in .csv format document, as shown in Figure 3-12 Figure 3-13. Figure 3-12 Export the log file Figure 3-13 Export the log file in .csv format Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 85: Chapter 4 Transceiver Verification

    Transceiver Verification his chapter describes how to verify the FPGA transceivers in the QSFP28 connector by using the test code provided in the Apollo Agilex board system Function of the Transceiver Test Code The transceiver test code is used to verify the transceiver channels for the QSFP28 connector through an external loopback method.

  • Page 86: Execute The Test Code

    Here are the procedures to perform transceiver channel test: 1. Copy Transceiver_Test folder to your local disk. 2. Install the Windows Subsystem for Linux (WSL) on your windows for execute the demo batch file, please refer link below install http://www.terasic.com.tw/wiki/Getting_Start_Install_WSL Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 87 Agilex board as shown in Figure 4-2. 5. Connect a USB cable to the Mini USB connector (J9) on the Apollo Agilex board and the Host Windows PC. 6. Power on the Apollo Agilex board. 7. Execute 'test.bat" in the Transceiver_Test folder under your local disk.
  • Page 88 Figure 4-3 Test result Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 89: Install Driver For The Board

    MAX 10, the FT232R for UART to USB for HPS. When the user connects the Mini USB cable to the Mini USB connector of the Apollo Agilex board, the “Device Manager” window on your Windows system should see three USB to UART devices as...
  • Page 90  Install driver for CP2105 To install the driver for CP2105, users can find it from the path: Tool\dashboard_gui\Driver in the Apollo Agilex system CD and copy it to the host PC. User can also download the driver from manufacturer's download site.
  • Page 91 Figure 5-2 The driver for CP2105 Figure 5-3 Completing device driver install After the driver installation of CP2105 is completed, two USB to UART ports can be Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 92 The FT232R chip is the USB to UART interface for HPS fabric. When the user's computer is connected to the Apollo Agilex board through the Mini USB cable for the first time, if the FT232R has no driver installed, the status on the “Device Manager”...
  • Page 93 After the driver has been correctly installed, the USB Serial Port is recognized as a port such as COM5 (Open the Device Manager to know which COM port assigned in your computer). Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...
  • Page 94 Figure 5-6 The USB to UART devices on the board Apollo-Agilex SoM www.terasic.com User Manual July 20, 2022...

  • Page 95: Chapter 6 Additional Information

    Here are the addresses where you can get help if you encounter problems:  Terasic Technologies No.80, Fenggong Rd., Hukou Township, Hsinchu County 303035. Taiwan Email: support@terasic.com Web: www.terasic.com Apollo Agilex Web: agilex-som.terasic.com  Revision History Date Version Changes 2022.07...

Table of Contents