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DDR4C_RZQ
Table 2-19 DDR4-D Bank Pin Assignments, Schematic Signal Names, and
Schematic
Signal Name
DDR4D_REFCLK_p
DDR4D_A0
DDR4D_A1
DDR4D_A2
DDR4D_A3
DDR4D_A4
DDR4D_A5
DDR4D_A6
DDR4D_A7
DDR4D_A8
DDR4D_A9
DDR4D_A10
DDR4D_A11
DDR4D_A12
DDR4D_A13
DDR4D_A14
DDR4D_A15
DDR4D_A16
DDR4D_BA0
DDR4D_BA1
DDR4D_BG0
DDR4D_BG1
DDR4D_CK[0]
MA27
User Manual
Calibrated pins for
OCT block
Functions
Description
DDR4D port
Reference Clock p
Address [0]
Address [1]
Address [2]
Address [3]
Address [4]
Address [5]
Address [6]
Address [7]
Address [8]
Address [9]
Address [10]
Address [11]
Address [12]
Address [13]
Address [14]
Address [15]
Address [16]
Bank Select [0]
Bank Select [1]
Bank Group Select
[0]
Bank Group Select
[1]
Clock p
57
1.2 V
I/O Standard
True Differential
Signaling
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
SSTL-12
DIFFERENTIAL 1.2V
SSTL
PIN_KJ37
Agilex Pin Number
PIN_MA44
PIN_KR45
PIN_KU44
PIN_KJ45
PIN_KF44
PIN_KU46
PIN_KR47
PIN_KF46
PIN_KJ47
PIN_KR49
PIN_KU48
PIN_KF48
PIN_KJ49
PIN_LR43
PIN_LW45
PIN_MA46
PIN_LR45
PIN_LN46
PIN_LW47
PIN_LN48
PIN_LR47
PIN_LH44
PIN_LH48
www.terasic.com
February 17,
2024
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