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2.9
PCI Express
The FPGA development board is designed to fit entirely into a PC motherboard with
x16 PCI Express slot. Utilizing built-in transceivers on an Agilex device, it is able to
provide a fully integrated PCI Express-compliant solution for multi-lane (x1, x4, x8 and
x16) applications. With the PCI Express hard IP block incorporated in the Agilex device,
it will allow users to implement simple and fast protocol, as well as saving logic
resources for logic application.
between the Agilex FPGA and PCI Express.
The PCI Express interface supports complete PCI Express Gen1 at 2.5Gbps/lane,
Gen2 at 5.0Gbps/lane, Gen3 at 8.0Gbps/lane, Gen4 at 16.0Gbps/lane and Gen5
protocol stack solution compliant to PCI Express base specification 5.0 that includes
PHY-MAC, Data Link, and transaction layer circuitry embedded in PCI Express hard IP
blocks.
Please note that it is a requirement that you connect the PCIe external power
connector 8-pin 12V DC power connector in the FPGA to avoid FPGA damage due to
insufficient power.
The PCIE_REFCLK_p[1:0] signal are driven from the PC motherboard on this board
through the PCIe edge connector or on-board PCIe clock generator. User can use
switch to choose wich clock soure are used as reference clock. Please see the section
2.3 : PCIe Clock Select Switch for detailed.
A DIP switch (SW4) is connected to the PCI Express to allow different configurations to
enable x1, x4, x8 or x16 PCIe lane. Please see the section 2.3 : Setup PCI Express
Control DIP switch for detailed.
Table 2-22
summarizes the PCI Express pin assignments of the signal names relative
to the Agilex FPGA.
MA27
User Manual
Figure 2-24
presents the pin connection established
68
www.terasic.com
February 17,
2024
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