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Terasic PCA3 User Manual

Pcie x4 cable adapter, for pcie gen 3
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Summary of Contents for Terasic PCA3

  • Page 2: Table Of Contents

    1.3 Getting Help ............................... 4 Chapter 2 Architecture ........................5 2.1 Layout and Components ..........................5 2.2 Block Diagram of the PCA3 card ....................... 6 Chapter 3 Card Components ......................8 3.1 PCIe Edge Connector ..........................8 3.2 PCIe Cable Connector ..........................10 3.3 LEDs .................................

  • Page 3: Chapter 1 Introduction

    Chapter 1 Introduction PCA3 (PCIe Cable Adapter, Gen 3) is a conversion card to connect boards with your host PC. It can support up to PCIe Gen 3 x4. Users with boards such as Terasic TR4 and TR5 can establish high-speed data transmission through this card and the PCIe cable via PCIe connector to any host PC.

  • Page 4: Features

    Figure 1- shows a photograph of the PCA3. Figure 1-2 Exterior View The key features of the card are listed below: • Up to 8.0Gbps PCIe 3.0 Serial Re-Driver • PCIe x4 Gen 3 • Adjustable receiver equalization • Adjustable transmitter amplitude and de-emphasis PCA3 User Manual www.terasic.com...

  • Page 5: Getting Help

    Here is information of how to get help if you encounter any problem: Terasic Technologies • Tel: +886-3-550-8800 • Email: support@terasic.com PCA3 User Manual www.terasic.com February 8, 2018...

  • Page 6: Chapter 2 Architecture

    Chapter 2 Architecture This chapter provides information about architecture and block diagram of the PCA3 card. The picture of the Terasic PCIe x4 Cable Adapter (PCA3) is shown in Figure 2-1 Figure 2-2. It depicts the layout of the card and indicates the locations of the connectors and key components.

  • Page 7: Block Diagram Of The Pca3 Card

    Figure 2-2 The PCA3 Card PCB and Component Diagram (bottom view) Figure 2-3 shows the block diagram of the PCA3 card. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 8 Figure 2-3 Block Diagram of PCA3 PCA3 User Manual www.terasic.com February 8, 2018...

  • Page 9: Chapter 3 Card Components

    Chapter 3 Card Components This chapter describes the specifications of the onboard components. This PCIe edge connector is used to connect the PCA3 with PC motherboard PCIe slot, as show Figure 3-1 Figure 3-2. Figure 3-1 PCA3 Edge Connector PCA3 User Manual www.terasic.com...

  • Page 10: February

    Figure 3-2 Plug the PCA3 into the PCIe slot of the Motherboard The pins are defined as shown in Table 3-1 with side A on the top of the center-line on the solder side of the card and side B on the bottom of the centerline on the component side of the card.

  • Page 11: Pcie Cable Connector

    RSVD Reserved PERn3 Lane 3 PRSNT2n Hot-Plug presence Ground detect Ground RSVD Reserved A PCIe cable connector is used to connect the PCIe x4 Cable and PCA cable connector, connect the PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 12 PCIe x4 Cable, as show Figure 3-3. Figure 3-3 PCIe x4 Cable and PCA3 To purchase the PCIe x4 Cable, please refer to the url: PCIe_Cable.terasic.com. Figure 3-4 shows the PCIe Cable connects PCA3 connector PCA3 User Manual www.terasic.com...
  • Page 13 Figure 3-4 PCIe Cable and PCA3 connector Connected Table 3-2 gives the wiring information of the PCIe Cable connector. Table 3-2 wiring information of the PCIe Cable connector Pin Numbers Name Description Ground reference for PCI Express transmitter Lanes PETp0...
  • Page 14 Express transmitter Lanes PERp2 Differential PCI Express receiver Lane 2 PERn2 Differential PCI Express receiver Lane 2 Ground reference for PCI Express transmitter Lanes PERp3 Differential PCI Express receiver Lane 3 PERn3 Differential PCI Express PCA3 User Manual www.terasic.com February 8, 2018...

  • Page 15: Leds

    4-lane repeater function, DS80PCI402 chip also supports some modifiable parameters, such as input equalization, internal Signal Detect Threshold and loopback function. These functions can be set up by some of the resistances on PCA3 card, Figure 3-5 shows the resistances setting. Table 3-4 lists pin configuration and function.
  • Page 16 Controls the loopback function Tie 1kΩ to GND = Root Complex Loopback (INA_n to OUTB_n) Float = Normal Operation Tie 1kΩ to VDD = End-point Loopback (INB_n to OUTA_n) SD_TH/RD_EN Controls the internal Signal Detect Threshold PCA3 User Manual www.terasic.com February 8, 2018...

  • Page 17: Chapter 4 Setup Example

    Chapter 4 Setup Example This chapter demonstrates how to use PCA3 daughtercard with FPGA host board. In the system CD, we provide demonstration projects for Terasic TR4 and TR5 FPGA board. We will introduce how to use PCA3 daughtercard and Terasic TR5 FPGA development board to communicate with the PC via PCIe interface.
  • Page 18 PCI Express application software on 64-bit Windows. The PCI Express driver incorporated in the DLL library is called TERASIC_PCIE_AVMM.dll. Users can develop their applications based on this DLL. The altera_pcie_win_driver.sys kernel driver is provided by Altera. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 19 1. Make sure the TR5 and the PC are both powered off. 2. Plug the PCIe adapter card(PCA3) into the PCIe slot on the PC motherboard. Use the PCIe cable to connect to the TR5 PCIE connector and the PCA3 (See...
  • Page 20 PCI Device item in the dialog, as shown in Figure 4-3. Move the mouse cursor to the PCI Device item and right click it to select the Update Driver Software... item. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 21 8. In the How do you want to search for driver software dialog, click Browse my computer 4-4. Click “OK” and then “Exit” to close the for driver software item, as shown in Figure installation program. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 22 9. In the Browse for driver software on your computer dialog, click the Browse button to specify the folder where altera_pcie_din_driver.inf is located, as shown in Figure 4-5 Click the Next button. Figure 4-5 Browse for driver software on your computer PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 23 , click the Install button. Figure 4-6 Click Install in the dialog of Windows Security 11. When the driver is installed successfully, the successfully dialog will appear, as shown in Figure 4-7. Click the Close button. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 24  TERASIC_PCIE_AVMM.h  TERASIC_PCIE_AVMM.DLL (64-bit DLL) Below lists the procedures to use the SDK files in users’ C/C++ project :  Create a 64-bit C/C++ project.  Include TERASIC_PCIE_AVMM.h in the C/C++ project. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 25 Users need to call PCIE_Close to release handle once the handle is no more used.  PCIE_Close Function: Close a handle associated to the PCIe card. Prototype: void PCIE_Close( PCIE_HANDLE hPCIE); Parameters: hPCIE: PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 26 Return TRUE if read data is successful; otherwise FALSE is returned.  PCIE_Write32 Function: Write a 32-bit data to the FPGA Board. Prototype: bool PCIE_Write32( PCIE_HANDLE hPCIE, PCIE_BAR PcieBar, PCIE_ADDRESS PcieAddress, DWORD dwData); Parameters: PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 27 Specify the byte number of data retrieved from FPGA. Return Value: Return TRUE if read data is successful; otherwise FALSE is returned.  PCIE_DmaWrite Function: Write data to the memory-mapped memory of FPGA board in DMA. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 28 Offset: Specify the target byte of offset in PCIe configuration table. pdwData: A 4-bytes buffer to retrieve the 32-bit data. Return Value: Return TRUE if read data is successful; otherwise FALSE is returned. PCA3 User Manual www.terasic.com February 8, 2018...

  • Page 29: Reference Design - Fundamental

     TERASIC_PCIE_AVMM.dll  Demonstration Setup 1. Use the PCIe cable to connect to the TR5 PCIE connector and PCIe adapter card as shown in Figure 4-9. Figure 4-9 FPGA board connect to PC PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 30 7. Type 0 followed by a ENTER key to select Led Control item, then input 15 (hex 0x0f) will make all led on as shown in Figure 4-12. If input 0(hex 0x00), all led will be PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 31 Figure 4-13. Figure 4-13 Screenshot of Button Status Report 9. Type-2 followed by an ENTER key to select DMA Testing item. The DMA test result will be reported as shown in Figure 4-14. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 32 10. Type 99 followed by an ENTER key to exit this test program  Development Tools  Quartus II 16.0  Visual C++ 2012  Demonstration Source Code Location  Quartus Project: Demonstrations\TR5\PCIE_Fundamental  Visual C++ Project: Demonstrations\TR5\PCIe_SW_KIT\PCIE_FUNDAMENTAL PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 33 Figure 4-15 Hardware block diagram of the PCIe reference design  Windows Based Application Software Design The application software project is built by Visual C++ 2012. The project includes the following major files: Name Description PCIE_FUNDAMENTAL.cpp Main program PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 34 The LED control is implemented by calling PCIE_Write32 API, as shown below: The button status query is implemented by calling the PCIE_Read32 API, as shown below: The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below: PCA3 User Manual www.terasic.com February 8, 2018...

  • Page 35: Pcie Reference Design - Ddr3

    3. Configure FPGA with PCIE_DDR3.sof by executing the test.bat. 4. Install PCIe driver if necessary. 5. Restart Windows 6. Make sure the Windows has detected the FPGA Board by checking the Windows Control panel. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 36 Figure 4-17 Screenshot of Link Info 9. Type 3 followed by the ENTER key to select DMA On-Chip Memory Test item. The DMA write and read test result will be reported as shown in Figure 4-18. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 37 The DMA write and read test result will be report as shown in Figure 4-19. Figure 4-19 Screenshot of DDR3 SOSIMM Memory DAM Test Result 11. Type 99 followed by the ENTER key to exit this test program. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 38 LED and monitor the Button Status, and the On-Chip memory and DDR3 SODIMM Memory are used for performing DMA testing. The PIO controllers,the On-Chip memory and DDR3 SODIMM Memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 39 Implement dynamically load for PCIE.h TERAISC_PCIE_AVMM.DLL TERASIC_PCIE_AVMM.h SDK library file, defines constant and data structure The main program PCIE_DDR3.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design. PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 40 The LED control is implemented by calling PCIE_Write32 API, as shown below: The button status query is implemented by calling the PCIE_Read32 API, as shown below: The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below: PCA3 User Manual www.terasic.com February 8, 2018...
  • Page 41 The pcie link information is implemented by PCIE_ConfigRead32 API, as shown below: PCA3 User Manual www.terasic.com February 8, 2018...

  • Page 42: Chapter 5 Appendix

    Chapter 5 Appendix Version Change Log V1.0 Initial Version (Preliminary) V1.1 Add section 1.1 package contents and modify Copyright © 2017 Terasic Technologies. All rights reserved. PCA3 User Manual www.terasic.com February 8, 2018...

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