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Terasic Agilex 7 FPGA Starter Kit User Manual

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Agilex 7 FPGA
1
www.terasic.com
1.1. Vu0Q
Starter Kit
May 18, 2023
User Manual

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Summary of Contents for Terasic Agilex 7 FPGA Starter Kit

  • Page 1 Agilex 7 FPGA www.terasic.com 1.1. Vu0Q Starter Kit May 18, 2023 User Manual...

  • Page 2: Table Of Contents

    Board Overview ................... 12 Configuration ..................13 Status and Setup Components ............17 Reset Devices ..................24 General User Input/Output ..............25 Clock Circuit ..................28 DDR4 SO-DIMM ................. 31 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 3 2.14 System Status Interface ..............67 Chapter 3 Dashboard GUI..............69 Driver Installed on Host ............... 69 Run Dashboard GUI ................72 Chapter 4 Additional Information ............84 Getting Help ..................84 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 4: Chapter 1 Overview

    (A7SK) and installation guide. General Description The Terasic Agilex 7 FPGA Starter Kit takes advantage of the latest Intel Agilex™ 7 FPGA F-Series devices with 2x F-Tile and from 600K to 2.7M logic elements options, offering 50% higher fabric performance and 40% lower power consumption than equivalent Stratix®...

  • Page 5: Key Features

    Key Features The following hardware is implemented on the Agilex 7 FPGA Starter Kit board:  Intel® Agilex™ F-Series  AGFB027R24C2E2VR2  2.7M logic elements (LEs)  287 Mb On-chip RAM (M20K and MLAB)  17,056 18-bit x 19-bit multipliers ...

  • Page 6: Block Diagram

    Figure 1-1 Block diagram of the Agilex 7 FPGA Starter Kit board 1.4. Board Power On The Agilex 7 FPGA Starter Kit board can be used in stand-alone or be installed to the Agilex 7 FPGA www.terasic.com Starter Kit...
  • Page 7 Figure 1-2 Board Power Control Switch  Install to Host When the Agilex 7 FPGA Starter Kit is installed on the Host via PCIe slot. Although the Host can provide power to Agilex 7 FPGA Starter Kit board via PCIe slot, but Terasic...
  • Page 8 This can prevent the power provided from Host unable to meet the power requirement of Agilex 7 FPGA Starter Kit. If the power supply to the board is insufficient, it may cause some components to be abnormal.

  • Page 9: Install Drivers For Usb Port

    Micro USB connector through the USB hub. The user only needs to connect the host with a USB cable to the board to realize these Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023...

  • Page 10: Board Protection

    Figure 1-5 The Micro USB port 2.1. Board Protection The temperature of Agilex 7 FPGA Starter Kit board will have a lot to do with the user's design code, chassis, and ambient temperature. When using Agilex 7 FPGA Starter Kit board in the server. Customers should pay attention to whether the temperature of Agilex 7 FPGA Starter Kit board is too high to avoid abnormal work for user’s design or even damage to the board.

  • Page 11: Mechanical Specifications

    In addition, the efficiency of the Agilex 7 FPGA Starter Kit cooling system will decrease with the aging of dust and fans, so customers should re-evaluate the cooling efficiency regularly.

  • Page 12: Chapter 2 Board Component

    Figure 2-1 Figure 2-2 is the top and bottom view of the Agilex 7 FPGA Starter Kit development board. It depicts the layout of the board and indicates the location of the connectors and key components. Users can refer to this figure for relative location of the connectors and key components.

  • Page 13: Configuration

    Agilex SoC FPGA and make the FPGA to run the user's logic or boot the HPS to run the OS. Below we will introduce more detailed information of AS mode, as well as other configuration information. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 14 QSPI flash to configure the FPGA including FPGA I / O and core configuration. HPS part of the boot can also be completed in this mode. Figure 2-4 shows the architecture of the AS mode of the Agilex 7 FPGA Starter Kit. Agilex 7 FPGA www.terasic.com Starter Kit...
  • Page 15 FPGA fabric after powering on. More details can be found in the user documentation: Intel® Agilex™ SoC FPGA Boot User Guide. The factory setting of the SoC boot of the Agilex 7 FPGA Starter Kit is the FPGA Configuration First Mode. The architecture is shown in the Figure 2-5.
  • Page 16 The factory SoC boot process of Apollo Agilex is summarized as follows: When the Agilex 7 FPGA Starter Kit is powered on, the SDM will read the configuration firmware and complete SDM initial form the QSPI flash according to the MSEL pin setting.

  • Page 17: Status And Setup Components

     Status LED The FPGA Board development board includes board-specific status LEDs to indicate board status. Please refer to Figure 2-6 Table 2-1 for the description of the LED indicator. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 18 (*1) Illuminates when the 3.3V power abnormal POWER_LEDR or power sequence process failed. (*1) Illuminates when the USB Blaster II circuit is JTAG_RX transmitting data Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 19 Description Default Reference On : Enable x1 presence detect SW4.1 PCIE_PRSNT2n_x1 Off: Disable x1 presence detect On : Enable x4 presence detect SW4.2 PCIE_PRSNT2n_x4 Off: Disable x4 presence detect Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 20 Figure 2-8 Position of slide switches SW6 and SW7 for Configuration Mode Table 2-3 MSEL Settings for supported configuration Scheme of the board FPGA Configuration MSEL2 MSEL1 MSEL0 Mode AS Fast (Default) Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 21 HPS or FMC+ connector. The JTAG chain on the board will not be able to form a closed loop and Quartus will not be able to detect the FPGA device. Figure 2-9 JTAG Bypass Switch Table 2-4 SW3 setting Board Signal Name Description Default Reference Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 22 Table 2-5 FPGA I/Os on the FMC+ connector which can be changed I/O standard to 1.2 or 1.5V FMC+ Pins which can modify I/O stadnard FMCP_HA_p[23..0] FMCP_HA_n[23..0] FMCP_HB_p[21..0] FMCP_HB_p[21..0] FMCP_HB_n[21..0] FMCP_CLK_M2C_p1 FMCP_CLK_M2C_n1 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 23 Figure 2-10 FMC and FMC+ I/O standard setting headers Table 2-6 JP3 Setting for FMC+ I/O standard JP3 Setting FMC I/O Standard 1.2V (Default) 1.5V Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 24: Reset Devices

    Figure 2-11). These buttons can reset FPGA, System MAX, HPS and FPGA respectively. Please refer to the following Table 2-7 for details. Figure 2-11 Rest devices of the board Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 25: General User Input/Output

    PCIE_PERST_n 1.2V PIN_BR43 PCIe reset General User Input/Output This section describes the user I/O interface of the FPGA. Figure 2-12 shows the position of all these components and interface. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 26 Schematic Board Agilex Signal Description Reference Standard Pin Number Name BUTTON0 High Logic Level when the button 1.2V PIN_DA9 is not pressed BUTTON1 1.2V PIN_CY8  User-Defined Dip Switch Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 27 2-13. GPIO_P0 ~ GPIO_P3 are bi-direction 1.2V GPIO. GPIO_CLK0 and GPIO_CLK1 are connected to FPGA dedicated clock input and can be configured as two single-ended clock signals. Table 2-11 shows the mapping of the Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 28: Clock Circuit

    The development board includes several oscillator (25/50/33.33/100/125 MHz) and two programmable clock generators. Figure 2-14 shows the default frequencies of on-board all external clocks going to the Agilex FPGA. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 29 Table 2-12 lists the clock source, signal names, default frequency and their corresponding Agilex device pin numbers. Table 2-12 Clock Source, Signal Name, Default Frequency, Pin Assignments and Functions Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 30 33.333 MHz LVDS PIN_DD36 clock for SODIMM DDR4 reference DDR4B_REFCLK_p 33.333 MHz LVDS PIN_U5 clock for on-chip devices (*1) Fan-out by Si53306 clock buffer (U73). (*2) Fan-out by Si53306 clock buffer (U74). Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 31: Ddr4 So-Dimm

    The DDR4 SO-DIMM Socket and on-board DDR4 can run at the fastest clock frequency of 1600MHz clock for a maximum theoretical bandwidth up to 170 Gbps. Figure 2-15 shows the connections between the DDR4 interface and Agilex SoC FPGA. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 32 Data [8] 1.2V POD PIN_J5 DDR4A_DQ9 Data [9] 1.2V POD PIN_K2 DDR4A_DQ10 Data [10] 1.2V POD PIN_F2 DDR4A_DQ11 Data [11] 1.2V POD PIN_J1 DDR4A_DQ12 Data [12] 1.2V POD PIN_K6 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 33 Data [42] 1.2V POD PIN_Y24 DDR4A_DQ43 Data [43] 1.2V POD PIN_Y20 DDR4A_DQ44 Data [44] 1.2V POD PIN_T24 DDR4A_DQ45 Data [45] 1.2V POD PIN_W19 DDR4A_DQ46 Data [46] 1.2V POD PIN_W23 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 34 PIN_L3 DIFFERENTIAL 1.2V DDR4A_DQS_n0 Data Strobe n[0] PIN_M4 DIFFERENTIAL 1.2V DDR4A_DQS1 Data Strobe p[1] PIN_G3 DIFFERENTIAL 1.2V DDR4A_DQS_n1 Data Strobe n[1] PIN_F4 DDR4A_DQS2 Data Strobe p[2] DIFFERENTIAL 1.2V PIN_A7 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 35 PIN_AB6 Data Bus Inversion DDR4A_DBI_n0 1.2V POD PIN_R3 Data Bus Inversion 1.2V POD DDR4A_DBI_n1 PIN_J3 Data Bus Inversion 1.2V POD DDR4A_DBI_n2 PIN_E7 Data Bus Inversion 1.2V POD DDR4A_DBI_n3 PIN_J9 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 36 Address [15]/ DDR4A_A15 SSTL-12 PIN_W3 CAS_n Address [16]/ DDR4A_A16 SSTL-12 PIN_Y4 RAS_n DDR4A_BA0 Bank Select [0] SSTL-12 PIN_T2 DDR4A_BA1 Bank Select [1] SSTL-12 PIN_W1 Bank Group Select DDR4A_BG0 SSTL-12 PIN_Y2 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 37 Calibrated pins for DDR4A_RZQ 1.2 V PIN_W5 OCT block Table 2-15 DDR4-B Bank Pin Assignments, Schematic Signal Names, and Functions Schematic Description I/O Standard Agilex Pin Number Signal Name Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 38 Data [29] 1.2V POD PIN_CK46 DDR4B_DQ30 Data [30] 1.2V POD PIN_CL43 DDR4B_DQ31 Data [31] 1.2V POD PIN_CK42 DDR4B_DQ32 Data [32] 1.2V POD PIN_CN37 DDR4B_DQ33 Data [33] 1.2V POD PIN_CP40 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 39 Data [63] 1.2V POD PIN_DE53 DDR4B_DQ64 Data [64] 1.2V POD PIN_DJ41 DDR4B_DQ65 Data [65] 1.2V POD PIN_DJ45 DDR4B_DQ66 Data [66] 1.2V POD PIN_DE41 DDR4B_DQ67 Data [67] 1.2V POD PIN_DF44 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 40 PIN_DC47 DIFFERENTIAL 1.2V DDR4B_DQS6 Data Strobe p[6] PIN_DD52 DIFFERENTIAL 1.2V DDR4B_DQS_n6 Data Strobe n[6] PIN_DC53 DIFFERENTIAL 1.2V DDR4B_DQS7 Data Strobe p[7] PIN_DH48 DDR4B_DQS_n7 Data Strobe n[7] DIFFERENTIAL 1.2V PIN_DJ49 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 41 Address [5] SSTL-12 PIN_DJ37 DDR4B_A6 Address [6] SSTL-12 PIN_DF36 DDR4B_A7 Address [7] SSTL-12 PIN_DE37 DDR4B_A8 Address [8] SSTL-12 PIN_DH34 DDR4B_A9 Address [9] SSTL-12 PIN_DJ35 DDR4B_A10 Address [10] SSTL-12 PIN_DF34 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 42 Command Input DDR4B_RESET_n Chip Reset 1.2 V PIN_DC43 DDR4 B port True Differential DDR4B_REFCLK_p PIN_DD36 Reference Clock p Signaling DDR4 B port True Differential DDR4B_REFCLK_n PIN_DD37 Reference Clock n Signaling Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 43: Qsfp28 Port

    Signal Name Number HSSI QSFP28_TX_P0 Transmitter data of channel 0 DIFFERENTIAL PIN_AV52 HSSI QSFP28_TX_N0 Transmitter data of channel 0 DIFFERENTIAL PIN_AU51 HSSI QSFP28_RX_P0 Receiver data of channel 0 DIFFERENTIAL PIN_AR55 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 44 DIFFERENTIAL PIN_AH54 HSSI QSFP28_TX_P3 Transmitter data of channel 3 DIFFERENTIAL PIN_AF52 HSSI QSFP28_TX_N3 Transmitter data of channel 3 DIFFERENTIAL PIN_AE51 HSSI QSFP28_RX_P3 Receiver data of channel 3 PIN_AC55 DIFFERENTIAL Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 45 3.0-V LVTTL PIN_B42 QSFP28_SDA 2-wire serial interface data 3.0-V LVTTL PIN_E39 QSFP28_LP_MODE Low Power Mode 3.0-V LVTTL PIN_E47 QSFP28_INTERRUPT_ Interrupt 3.0-V LVTTL PIN_A45 QSFP28_MOD_PRS_n Module Present 3.0-V LVTTL PIN_A39 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 46: Pci Express

    (SW4) is connected to the PCI Express to allow different configurations to enable x1, x4 or x8 PCIe lane. Table 2-17 summarizes the PCI Express pin assignments of the signal names relative to the Agilex FPGA. Figure 2-17 PCI Express pin connection Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 47 HIGH Speed PCIE_TX_p6 Add-in card transmit bus PIN_BF52 Differential I/O HIGH Speed PCIE_TX_n6 Add-in card transmit bus PIN_BE51 Differential I/O HIGH Speed PCIE_TX_p7 Add-in card transmit bus PIN_BB52 Differential I/O Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 48 PIN_BD54 Differential I/O HIGH Speed PCIE_RX_p7 Add-in card receive bus PIN_AW55 Differential I/O HIGH Speed PCIE_RX_n7 Add-in card receive bus PIN_AY54 Differential I/O PCIE_CLKREQ_n Clock request signal 1.2V PIN_A37 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 49: Fmc+ Connector

    Hot plug detect x8 PCIe slot PCIE_PRSNT2n_x8 enabled using SW6 dip switch 2.10 FMC+ Connector In addition to an FMC connector on the Agilex 7 FPGA Starter Kit, there is an FMC + connector for expanding FPGA I/Os (See Figure 2-18). The main difference between...
  • Page 50 CV16 FMCP_LA_n17 LA_N17 CLK_B_2D_1N CW17  Power Supply The Agilex 7 FPGA Starter Kit provides 12V, 3.3V and 1.2V(VADJ) power through FMC+ port. Table 2-19 indicates the maximum power consumption for the FMC+ connector. Agilex 7 FPGA www.terasic.com Starter Kit...
  • Page 51 FMC+ connector so that the JTAG device on the user's FMC+ daughter card can be joined with JTAG chain on the Agilex 7 FPGA Starter Kit. Users can enable this feature through the switch (SW3.1) on the Agilex 7 FPGA Starter Kit. In the board's default setting, the JTAG interface of the FMC connector is bypassed to keep the Agilex 7 FPGA Starter Kit JTAG chain to maintain close loop.
  • Page 52 FMC+ connector pin assignments, signal names and function. Figure 2-19 FMC+ pin out table Table 2-21 FMCP Connector Pin Assignments, Signal Names and Functions Signal Name FPGA Pin Description I/O Standard Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 53 FMCP HA bank data p9 1.2V or 1.5V *(1) FMCP_HA_p[10] PIN_DH22 FMCP HA bank data p10 1.2V or 1.5V *(1) FMCP_HA_p[11] PIN_CY26 FMCP HA bank data p11 1.2V or 1.5V Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 54 FMCP HA bank data n12 1.2V or 1.5V *(1) FMCP_HA_n[13] PIN_DE21 FMCP HA bank data n13 1.2V or 1.5V *(1) FMCP_HA_n[14] PIN_DE27 FMCP HA bank data n14 1.2V or 1.5V Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 55 FMCP HB bank data p15 1.2V or 1.5V *(1) FMCP_HB_p[16] PIN_CP32 FMCP HB bank data p16 1.2V or 1.5V *(1) FMCP_HB_p[17] PIN_CV34 FMCP HB bank data p17 1.2V or 1.5V Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 56 PIN_CN35 FMCP HB bank data n20 1.2V or 1.5V *(1) FMCP_HB_n[21] PIN_CR35 FMCP HB bank data n21 1.2V or 1.5V FMCP_LA_p[0] PIN_DF10 FMCP LA bank data p0 1.2 V Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 57 1.2 V FMCP_LA_p[25] PIN_CT18 FMCP LA bank data p25 1.2 V FMCP_LA_p[26] PIN_CV18 FMCP LA bank data p26 1.2 V FMCP_LA_p[27] PIN_CT16 FMCP LA bank data p27 1.2 V Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 58 1.2 V FMCP_LA_n[18] PIN_CR15 FMCP LA bank data n18 1.2 V FMCP_LA_n[19] PIN_CW13 FMCP LA bank data n19 1.2 V FMCP_LA_n[20] PIN_CR13 FMCP LA bank data n20 1.2 V Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 59 High Speed FMCP_DP_C2M_p[2] FPGA transceiver Differential I/O PIN_AU7 Transmit pair p3 of the High Speed FMCP_DP_C2M_p[3] FPGA transceiver Differential I/O FMCP_DP_C2M_p[4] PIN_AV4 Transmit pair p4 of the High Speed Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 60 FPGA transceiver Differential I/O PIN_AN1 Receiver pair p2 of the High Speed FMCP_DP_M2C_p[2] FPGA transceiver Differential I/O PIN_AU1 Receiver pair p3 of the High Speed FMCP_DP_M2C_p[3] FPGA transceiver Differential I/O Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 61 1.2-V SSTL module to positive PIN_CK22 Reference clock from True Differential FMCP_REFCLK_M2C_p mezzanine module to Signaling carrier card positive *(2) FMCP_GA[0] PIN_DA17 FMCP geographical 3.3 V Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 62: Usb To Uart

    HPS fabric through the UART interface. The other one is to connect to the system MAX10 device. It allows users to monitor various status of the board such as temperature and voltage value from the Host. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 63 Figure 2-21 Connections between the HPS of Apollo Agilex and FT232R Chip Table 2-22 Pin Assignment of UART Interface Signal Name FPGA Pin No. Description I/O Standard HPS_UART_RX PIN_AF8 HPS UART Receiver 1.8V HPS_UART_TX PIN_AT12 HPS UART Transmitter 1.8V Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 64: Micro Sd Card Socket

    (such as a fan failure condition), the FPGA power will be cut to protect the board. See chapter 3 for details. Terasic also provide a “board information IP” that allow user can place it in the Agilex FPGA to read these board status. Please refer to the section 2.5 of the demonstration manual.

  • Page 65: Gigabit Ethernet

    HPS, Gigabit Ethernet PHY, and RJ-45 connector. For more information about the KSZ9031RN PHY chip and its datasheet, as well as the application notes, which are available on the manufacturer’s website. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 66 Link / Activity (RX, TX) Table 2-25 Pin Assignment of Gigabit Ethernet PHY Signal Name FPGA Pin No Description I/O Standard HPS_ENET_TX_CTL PIN_AL13 GMII and MII transmit enable 1.8V Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 67: System Status Interface

    Finally, the board status also can be read on the Agilex FPGA side via the SPI interface connected to the System MAX10 FPGA. Terasic had provided a “board information IP” that allow user can place it in the FPGA to read these board status. Please refer to the section 5.4...
  • Page 68 Signal Name Number Serial Clock, SPI master output to PIN_D54 INFO_SPI_SCLK 1.2V salve. INFO_SPI_MISO Master input. 1.2V PIN_E51 INFO_SPI_MOSI Master output. 1.2V PIN_E53 INFO_SPI_CS_n Slave Select, Master output. 1.2V PIN_E49 Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 69: Chapter 3 Dashboard Gui

    To use the dashboard system, users need to install the USB to UART driver on the host first, so that user can establish a connection with the Agilex 7 FPGA Starter Kit board. This section will describe how to install USB to UART driver on the windows OS host.
  • Page 70 Kit system CD and copy it to the Host.  Connection Setting Connect the Micro USB connector of the Agilex 7 FPGA Starter Kit board to the Host USB port through Micro USB cable. Figure 3-2 Connection setup for using dashboard system Connect power to the Agilex 7 FPGA Starter Kit board.
  • Page 71 Copy the device driver (System CD\Tool\dashboard_gui\Driver) to the Host and install it, as shown in Figure 3-4. Please note that the COM Port number is different in different Host. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 72: Run Dashboard Gui

    FPGA Starter Kit system CD and copy it to the Host. Execute the Dashboard.exe, a window will show as Figure 3-6. It will describe the detail functions as below. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 73 3-7, there is a Start button at the bottom-left of the GUI window. Click it to run the program (Start will change to Stop), it will show the Agilex 7 FPGA Starter Kit board status. Users can press Stop button to stop the status data transmission and display.
  • Page 74  FPGA Status: As shown in Figure 3-8, it will show the status LED number on the Agilex 7 FPGA Starter Kit board. The definitions of these indicator LEDs are as follows:  FPGA_SD_LED When this status is shown in green on the GUI, it means that the FPGA temperature or the board temperature exceeds 95 degrees or the power consumption exceeds 180W.
  • Page 75  FPGA/Board/Transceiver Temperature: The Dashboard GUI will real-time show the Agilex 7 FPGA Starter Kit board’s ambient temperature (Board and Board2 data in the GUI) and FPGA and FPGA’s transceiver (F-Tile 12C and F-Tile 13A) temperature. Users can know the board’s temperature status in time. The...
  • Page 76 Figure 3-9 Temperature section Figure 3-10 Location of the board’s ambient temperature Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 77  Fan RPM: It displays the real-time speed of the two fans (Fan and Fan2 in the GUI) on the Agilex 7 FPGA Starter Kit board, as shown in Figure 3-11. Figure 3-11 FAN RPM section  12V/Core Power monitor: It displays the real-time 12V/Core Power (0.8V~0.85V) voltage and consumption current on the Agilex 7 FPGA Starter Kit board.
  • Page 78 Figure 3-12 Select “12V Power” Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 79 Sampling Speed: It can change interval time that the Dashboard GUI sample the board status. Users can adjust it to 1s/10s/1min/Full Speed (0.1s) to sample the board status, as shown in Figure 3-14 Figure 3-15. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 80 Note that to active these functions, you will need to stop obtaining the board status (i.e. Don’t Press “Start” button or Press "Stop" button) in the GUI. Detailed introductions of these functions are described in below. Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 81 “Auto shutdown status” because the FPGA temperature is too high or the fan speed is abnormal.  Board Information: Click the “Board Information” to get the current MAX 10 FPGA software version and the Agilex 7 FPGA Starter Kit board version, as shown in Figure 3-17.
  • Page 82 Log File: Click the Export in the File page to save the board temperature, fan speed and voltage data in .csv format document, as shown in Figure 3-18 Figure 3-19. Figure 3-18 Export the log file Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...
  • Page 83 Figure 3-19 Export the log file in .csv format Agilex 7 FPGA www.terasic.com Starter Kit May 18, 2023 User Manual...

  • Page 84: Chapter 4 Additional Information

    Here are the addresses where you can get help if you encounter problems:  Terasic Technologies No.80, Fenggong Rd., Hukou Township, Hsinchu County 303035. Taiwan Email: support@terasic.com Web: www.terasic.com Agilex 7 FPGA Starter Kit Web: A7SK.terasic.com  Revision History Date Version Changes 2023.05 First publication ...

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