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Table 2-7 Reset Devices Pin Assignments, Schematic Signal Names, and
Part
Number
PB5
PB6
PB4
PB7
PB8
PB9
2.5
General User Input/Output
This section describes the user I/O interface of the FPGA.
User Defined Push-buttons
As shown in
Figure
(one for HPS farbric) that allow users to interact with the Agilex device. Each
push-button provides a high logic level or a low logic level when it is not pressed or
pressed, respectively.
corresponding Agilex device pin numbers.
MA27
User Manual
Functions
Schematic
Signal Name
CPU_RST
MAX_RST
HPS_COLD_RST
PCIE_RST
CXF_RST
CXL_RST
2-15, the FPGA board includes three user defined push-buttons
Table 2-8
lists the board references, signal names and their
29
Agilex
I/O
Pin
Standard
Number
1.2V
PIN_B47
--
--
--
--
1.2V
PIN_CD58
1.2V
PIN_JL61
1.2V
PIN_HY33
Application
This button can
be used for rest
FPGA
For resetting
System MAX10
For resetting
System HPS
Fabric
Push to reset
PCIe bus
Push to reset
CXF bus
Push to reset
CXL bus on the
MCIO
connectors
www.terasic.com
February 17,
2024
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