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Terasic Mercury A2700 User Manual

Accelerator card
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MA27
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www.terasic.com
1.1. Vu0Q
User Manual
February 17,
2024

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Summary of Contents for Terasic Mercury A2700

  • Page 1 MA27 www.terasic.com 1.1. Vu0Q User Manual February 17, 2024...

  • Page 2: Table Of Contents

    Board Component ..............12 Board Overview ................... 12 Configuration ..................13 Status and Setup Components ............18 Reset Devices ..................28 General User Input/Output ..............29 Clock Circuit ..................35 DDR4 SDRAM Interface ..............39 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 3 Programming Bit Stream File Into QSPI Flash ........89 Restore Factory Settings ..............92 Chapter 4 Dashboard GUI ..............94 Driver Installed on Host ............... 94 Run Dashboard GUI ................97 Chapter 5 Additional Information............108 Getting Help ..................108 MA27 www.terasic.com User Manual February 17, 2024...

  • Page 4: Chapter 1 Overview

    As the first Terasic accelerator that provides PCIe 5.0 x16 and Compute Express Link (CXL) support, the Mercury A2700 accelerator card enables 2X higher bandwidth compared with PCIe 4.0 interface for higher data throughput, as well as high-speed,...
  • Page 5 One: DDR4 SO-DIMM Socket shared with FPGA  Gigabit Ethernet PHY with RJ45 Port  UART to USB Port  USB OTG with MicroUSB Connector  LED x1, Button x1, Cold Reset Button MA27 www.terasic.com User Manual February 17, 2024...

  • Page 6: Block Diagram

    1.3. Block Diagram Figure 1-1 shows the block diagram of the Mercury A2700 Accelerator Card. To provide maximum flexibility for the users, all key components are connected to the Agilex® FPGA device. Thus, users can configure the FPGA to implement any system design.

  • Page 7: Board Power On

    1.4. Board Power On The Mercury A2700 Accelerator Card can be used in stand-alone or be installed to the Host through PCIe slot. This section will introduce how to power on the board and the information that user should notice in these two modes.
  • Page 8 2x4 ATX power connector) to the board. This can prevent the power provided from Host unable to meet the power requirement of Mercury A2700 Accelerator Card. If the power supply to the board is insufficient, it may cause some components to be abnormal.

  • Page 9: Install Drivers For Usb Port

    USB cable to the board to realize these three functions. At the same time, some drivers need to be installed on the host to use these functions. Users can refer to the following steps. MA27 www.terasic.com User Manual February 17, 2024...

  • Page 10: Board Protection

    Figure 1-5 The Micro USB port 2.1. Board Protection The temperature of Mercury A2700 Accelerator Card will have a lot to do with the user's design code, chassis, and ambient temperature. When using Mercury A2700 Accelerator Card in the server. Customers should pay attention to whether the temperature of Mercury A2700 Accelerator Card is too high to avoid abnormal work for user’s design or even damage to the board.

  • Page 11: Mechanical Specifications

    In addition, the efficiency of the Mercury A2700 Accelerator Card cooling system will decrease with the aging of dust and fans, so customers should re-evaluate the cooling efficiency regularly. 2.2. Mechanical Specifications Figure 1-6 shows the Mechanical Layout of Mercury A2700 Accelerator Card. The unit of the Mechanical Layout is millimeter (mm).

  • Page 12: Chapter 2 Board Component

    Chapter 2 Board Component his chapter introduces all the important components on the Mercury A2700 Accelerator Card. Board Overview Figure 2-1 Figure 2-2 is the top and bottom view of the Mercury A2700 Accelerator Card development board. It depicts the layout of the board and indicates the location of the connectors and key components.

  • Page 13: Configuration

    Setup Configure Mode part of the section 2.3.  Avalon-ST x8 (MSEL[2:0] = 3’b110/Default Setting)  JTAG Mode (MSEL[2:0] = 3’b111 Configure the FPGA using the on-bo ard USB Blaster II).  Active Serial Fast mode (MSEL[2:0] = 3’b001) MA27 www.terasic.com User Manual February 17, 2024...
  • Page 14 On DE10-Agilex board, the data bus width of Avalon-ST mode is 8-bit (Avalon-ST x 8 mode). To set board to Avalon-ST mode, users need to set MSEL[2:0] to "110" (See Setup Configure Mode part of the section 2.3). For how to program the configuration MA27 www.terasic.com User Manual February 17, 2024...
  • Page 15 Launch Quartus Prime programmer and make sure the USB-Blaster II is detected.  In Quartus Prime Programmer, add the configuration bit stream file (.sof), check the associated “Program/Configure” item, and click “Start” to start MA27 www.terasic.com User Manual February 17, 2024...
  • Page 16 QSPI flash to configure the FPGA including FPGA I / O and core configuration. Figure 2-5 shows the architecture of the AS mode of the Mercury A2700 Accelerator Card. Figure 2-5 AS mode for the Mercury A2700 Accelerator Card For more information on the configuration of Intel Agilex®...
  • Page 17 The factory setting of the SoC boot of the Mercury A2700 Accelerator Card is the FPGA Configuration First Mode. The architecture is shown in the Figure 2-6. Two storage mediums are used. The system needs QSPI flash on Apollo Agilex as SDM flash for booting.

  • Page 18: Status And Setup Components

    The factory SoC boot process of Apollo Agilex is summarized as follows: When the Mercury A2700 Accelerator Card is powered on, the SDM will read the configuration firmware and complete SDM initial form the QSPI flash according to the MSEL pin setting. Then, the SDM will configure the FPGA I/O and core (full configuration).
  • Page 19 Illuminates when the 3.3V power good and POWER_LEDG power sequence process finished. (*1) Illuminates when the 3.3V power abnormal POWER_LEDR or power sequence process failed. (*1) MA27 www.terasic.com User Manual February 17, 2024...
  • Page 20  Setup PCI Express Control DIP switch The PCI Express Control DIP switch (SW8) is provided to enable or disable different configurations of the PCIe Connector (See Figure 2-8). Table 2-2 lists the switch controls and description. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 21 SW4.2 PCIE_PRSNT2n_x4 Off: Disable x4 presence detect On : Enable x8 presence detect SW4.3 PCIE_PRSNT2n_x8 Off: Disable x8 presence detect On : Enable x16 presence detect SW4.4 PCIE_PRSNT2n_x16 Off: Disable x16 presence detect MA27 www.terasic.com User Manual February 17, 2024...
  • Page 22 FPGA. The board supports Avalon-ST x8 and Fast AS mode, please set MSEL[2:0] for your desired mode as shown in Figure 2-9. The default setting mode is Avalon-ST x8 mode. Figure 2-9 Position of slide switches SW5 and SW4 for Configuration Mode MA27 www.terasic.com User Manual February 17, 2024...
  • Page 23 FPGA will read the factory default code in the flash to boot the FPGA.. Table 2-4 Setting for Factory image switch Board Signal Name Description Default Reference 1 : Factory page image FACTORY_LOAD 0: User page image Figure 2-10 Factory Image Switch MA27 www.terasic.com User Manual February 17, 2024...
  • Page 24 JTAG device on that interface. The JTAG chain on the board will not be able to form a closed loop and Quartus will not be able to detect the FPGA device. Figure 2-11 JTAG Bypass Switch MA27 www.terasic.com User Manual February 17, 2024...
  • Page 25 The PCIe Clock Select Switch is mainly used to control the reference clock source of PCIe applications sent to FPGA transceivers. Figure 2-12 is the block diagram of the reference clocks distribution on the board for PCIe applications. As shown in the figure, MA27 www.terasic.com User Manual February 17, 2024...
  • Page 26 Figure 2-13 shows the position of SW6 on the board and the switch definition. For detailed settings of SW6, please refer to Table 2-6. Figure 2-12 Block diagram of the PCIe clock application MA27 www.terasic.com User Manual February 17, 2024...
  • Page 27 ON : The reference clock for to FPGA (PCIE_REFCLK_14C_p/n[1:0]) will be came from PCIe golden finger. SW6.2 PCIE_REFCLK_SEL OFF: The reference clock for to FPGA (PCIE_REFCLK_14C_p/n[1:0]) will be came from on-board PCIe clock generator. MA27 www.terasic.com User Manual February 17, 2024...

  • Page 28: Reset Devices

    The board provides 4 reset buttons for different system reset situations (see Figure 2-14). These buttons can reset FPGA, System MAX, HPS and FPGA respectively. Please refer to the following Table 2-7 for details. Figure 2-14 Rest devices of the board MA27 www.terasic.com User Manual February 17, 2024...

  • Page 29: General User Input/Output

    Table 2-8 lists the board references, signal names and their corresponding Agilex device pin numbers. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 30 Signal Description Reference Standard Pin Number Name KEY0 BUTTON0 1.2V PIN_U47 KEY1 BUTTON1 High Logic Level when the button 1.2V PIN_N47 is not pressed HPS Push 1.2V PIN_N13 Bitton  User-Defined Dip Switch MA27 www.terasic.com User Manual February 17, 2024...
  • Page 31 5-pin LED bracket connector is reserved for connecting expanded LEDs. Figure 2-17 shows the circuit for the connectors and TTable 2-11 list of the connector pin names on the FPGA that are connected to the LEDs. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 32 LED1 LED1 1.2V PIN_J47 port turns the LED ON. LED2 LED2 1.2V PIN_W50 Driving a logic 1 on the I/O LED3 LED3 1.2V PIN_N51 port turns the LED OFF. HPS_LED HPS_LED 1.2V PIN_BJ27 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 33 1.2V GPIO. GPIO_CLK0 and GPIO_CLK1 are connected to FPGA dedicated clock input and can be configured as two single-ended clock signals. Table 2-12 shows the mapping of the FPGA pin assignments to the 2x5 GPIO header. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 34 Figure 2-18 2x5 expansion header Figure 2-19 Pin-out of 2x5 expansion header MA27 www.terasic.com User Manual February 17, 2024...

  • Page 35: Clock Circuit

    Bi-direction 1.2V GPIO Clock Circuit The development board includes several oscillator (25/50/33.33/100/125 MHz) and two programmable clock generators. Figure 2-20 shows the default frequencies of on-board all external clocks going to the Agilex FPGA. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 36 DDR4 SODIMMs. Two UFL connectors provide two external single-ended clock inputs or one external differential clock inputs. One oscillator provides a 125 MHz clock used as configuration MA27 www.terasic.com User Manual February 17, 2024...
  • Page 37 156.25 QSFPDDA_REFCLK_p LVDS PIN_HJ68 QSFP-DD A port 156.25 QSFPDDB_REFCLK_p LVDS PIN_JD74 QSFP-DD B port 156.25 Reserved for QSFPDDRSV_REFCLK_p LVDS PIN_HL74 QSFP-DD port CLK_30M72 30.72MHz 1.2V PIN_KJ27 Reserved DDR4A_REFCLK_p 33.333 LVDS PIN_AA31 DDR4 reference MA27 www.terasic.com User Manual February 17, 2024...
  • Page 38 Figure 2-21 U.FL clock input signal level setting Table 2-14 lists the programming clock generator (Si5397A and for QSFP-DD interface) control pin, signal names, I/O standard and their corresponding Agilex device pin numbers. MA27 www.terasic.com User Manual February 17, 2024...

  • Page 39: Ddr4 Sdram Interface

    (HPS). If HPS EMIF is not used in a system, the DDR4 SO-DIMM Socket A can be used for the EMIF of the FPGA. Table 2-15 shows the maximum capacity and associated running speed for each DDR4 SO-DIMM socket. The maximum capacity of MA27 www.terasic.com User Manual February 17, 2024...
  • Page 40 8GB @ 2666MTS 32GB Maximal Capacity 16GB @ 2666MTS 32GB @ 2400MTS 112GB Maximal Capacity with 16GB @ 2666MTS 16GB @ 2666MTS 64GB 2666MTS Figure 2-22 Connection between the DDR4 and Agilex FPGA MA27 www.terasic.com User Manual February 17, 2024...
  • Page 41 SSTL-12 PIN_AN29 CAS_n Address [16]/ DDR4A_A16 SSTL-12 PIN_AK30 RAS_n DDR4A_BA0 Bank Select [0] SSTL-12 PIN_AD28 DDR4A_BA1 Bank Select [1] SSTL-12 PIN_AN27 Bank Group Select DDR4A_BG0 SSTL-12 PIN_AK28 Bank Group Select DDR4A_BG1 SSTL-12 PIN_AV37 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 42 DDR4A_DQS_n1 Data Strobe n[1] PIN_D15 DIFFERENTIAL 1.2V DDR4A_DQS_n2 Data Strobe n[2] PIN_D26 DIFFERENTIAL 1.2V DDR4A_DQS_n3 Data Strobe n[3] PIN_D32 DIFFERENTIAL 1.2V DDR4A_DQS_n4 Data Strobe n[4] PIN_L38 DIFFERENTIAL 1.2V DDR4A_DQS_n5 Data Strobe n[5] PIN_AD42 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 43 1.2V POD PIN_H28 DDR4A_DQ23 Data [23] 1.2V POD PIN_J27 DDR4A_DQ24 Data [24] 1.2V POD PIN_B29 DDR4A_DQ25 Data [25] 1.2V POD PIN_D30 DDR4A_DQ26 Data [26] 1.2V POD PIN_J33 DDR4A_DQ27 Data [27] 1.2V POD PIN_D34 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 44 1.2V POD PIN_AD34 DDR4A_DQ57 Data [57] 1.2V POD PIN_AA37 DDR4A_DQ58 Data [58] 1.2V POD PIN_AN33 DDR4A_DQ59 Data [59] 1.2V POD PIN_AK34 DDR4A_DQ60 Data [60] 1.2V POD PIN_AD38 DDR4A_DQ61 Data [61] 1.2V POD PIN_AN37 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 45 PIN_AN35 Data Bus Inversion DDR4A_DBI_n8 1.2V POD PIN_BC29 DDR4A_CS_n Chip Select SSTL-12 PIN_BC37 DDR4A_RESET_n Chip Reset 1.2 V PIN_AT38 On Die DDR4A_ODT SSTL-12 PIN_AV35 Termination Command and DDR4A_PAR Address Parity SSTL-12 PIN_BF34 Input MA27 www.terasic.com User Manual February 17, 2024...
  • Page 46 PIN_AT64 DDR4B_A13 Address [13] SSTL-12 PIN_AG65 DDR4B_A14 Address [14] SSTL-12 PIN_AK66 DDR4B_A15 Address [15] SSTL-12 PIN_AV65 DDR4B_A16 Address [16] SSTL-12 PIN_AT66 DDR4B_BA0 Bank Select [0] SSTL-12 PIN_AK70 DDR4B_BA1 Bank Select [1] SSTL-12 PIN_AV68 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 47 DDR4B_DQS6 Data Strobe p[6] PIN_BJ59 DIFFERENTIAL 1.2V DDR4B_DQS7 Data Strobe p[7] PIN_AV59 DIFFERENTIAL 1.2V DDR4B_DQS8 Data Strobe p[8] PIN_B55 DIFFERENTIAL 1.2V DDR4B_DQS_n0 Data Strobe n[0] PIN_AT48 DDR4B_DQS_n1 Data Strobe n[1] DIFFERENTIAL 1.2V PIN_AD54 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 48 1.2V POD PIN_AN55 DDR4B_DQ14 Data [14] 1.2V POD PIN_AA55 DDR4B_DQ15 Data [15] 1.2V POD PIN_AD52 DDR4B_DQ16 Data [16] 1.2V POD PIN_BC51 DDR4B_DQ17 Data [17] 1.2V POD PIN_AV51 DDR4B_DQ18 Data [18] 1.2V POD PIN_AT56 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 49 1.2V POD PIN_AK62 DDR4B_DQ48 Data [48] 1.2V POD PIN_BV62 DDR4B_DQ49 Data [49] 1.2V POD PIN_CA61 DDR4B_DQ50 Data [50] 1.2V POD PIN_CA57 DDR4B_DQ51 Data [51] 1.2V POD PIN_BV58 DDR4B_DQ52 Data [52] 1.2V POD PIN_BM62 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 50 Data Bus Inversion DDR4B_DBI_n3 1.2V POD PIN_AN47 Data Bus Inversion DDR4B_DBI_n4 1.2V POD PIN_U55 Data Bus Inversion DDR4B_DBI_n5 1.2V POD PIN_AN59 Data Bus Inversion DDR4B_DBI_n6 1.2V POD PIN_CA59 DDR4B_DBI_n7 Data Bus Inversion 1.2V POD PIN_BC59 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 51 True Differential DDR4C_REFCLK_p PIN_KU36 Reference Clock p Signaling DDR4C_A0 Address [0] SSTL-12 PIN_LH42 DDR4C_A1 Address [1] SSTL-12 PIN_LL43 DDR4C_A2 Address [2] SSTL-12 PIN_KW43 DDR4C_A3 Address [3] SSTL-12 PIN_LB42 DDR4C_A4 Address [4] SSTL-12 PIN_LH40 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 52 DDR4C_CKE[0] Clock Enable pin SSTL-12 PIN_KF40 DDR4C_CKE[1] Clock Enable pin SSTL-12 PIN_KJ41 DIFFERENTIAL 1.2V DDR4C_DQS0 Data Strobe p[0] PIN_LH34 DIFFERENTIAL 1.2V DDR4C_DQS1 Data Strobe p[1] PIN_MH30 DIFFERENTIAL 1.2V DDR4C_DQS2 Data Strobe p[2] PIN_MH11 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 53 Data Strobe n[8] PIN_LL29 DDR4C_DQ0 Data [0] 1.2V POD PIN_LB32 DDR4C_DQ1 Data [1] 1.2V POD PIN_LB36 DDR4C_DQ2 Data [2] 1.2V POD PIN_LL33 DDR4C_DQ3 Data [3] 1.2V POD PIN_LH32 DDR4C_DQ4 Data [4] 1.2V POD PIN_KW33 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 54 1.2V POD PIN_LW35 DDR4C_DQ34 Data [34] 1.2V POD PIN_LW31 DDR4C_DQ35 Data [35] 1.2V POD PIN_LR31 DDR4C_DQ36 Data [36] 1.2V POD PIN_LR35 DDR4C_DQ37 Data [37] 1.2V POD PIN_LN36 DDR4C_DQ38 Data [38] 1.2V POD PIN_MA32 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 55 1.2V POD PIN_LH26 DDR4C_DQ68 Data [68] 1.2V POD PIN_LB26 DDR4C_DQ69 Data [69] 1.2V POD PIN_LL27 DDR4C_DQ70 Data [70] 1.2V POD PIN_LB30 DDR4C_DQ71 Data [71] 1.2V POD PIN_KW31 DDR4C_DBI_n0 Data Bus Inversion 1.2V POD PIN_LB34 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 56 SSTL-12 PIN_KJ39 Input Register ALERT_n DDR4C_ALERT_n 1.2 V PIN_KU32 output Activation DDR4C_ACT_n SSTL-12 PIN_KJ43 Command Input Chip Temperature DDR4C_EVENT_n 1.2 V PIN_JY26 Event DDR4C_C[0] Chip ID SSTL-12 PIN_KC37 DDR4C_C[1] Chip ID SSTL-12 PIN_JY36 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 57 SSTL-12 PIN_LN46 DDR4D_BA0 Bank Select [0] SSTL-12 PIN_LW47 DDR4D_BA1 Bank Select [1] SSTL-12 PIN_LN48 Bank Group Select DDR4D_BG0 SSTL-12 PIN_LR47 Bank Group Select DDR4D_BG1 SSTL-12 PIN_LH44 DIFFERENTIAL 1.2V DDR4D_CK[0] Clock p PIN_LH48 SSTL MA27 www.terasic.com User Manual February 17, 2024...
  • Page 58 DDR4D_DQS_n0 Data Strobe n[0] PIN_LL53 DIFFERENTIAL 1.2V DDR4D_DQS_n1 Data Strobe n[1] PIN_MK61 DIFFERENTIAL 1.2V DDR4D_DQS_n2 Data Strobe n[2] PIN_MK55 DIFFERENTIAL 1.2V DDR4D_DQS_n3 Data Strobe n[3] PIN_MA58 DDR4D_DQS_n4 Data Strobe n[4] DIFFERENTIAL 1.2V PIN_MK49 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 59 1.2V POD PIN_MD52 DDR4D_DQ20 Data [20] 1.2V POD PIN_MC57 DDR4D_DQ21 Data [21] 1.2V POD PIN_MC53 DDR4D_DQ22 Data [22] 1.2V POD PIN_MK53 DDR4D_DQ23 Data [23] 1.2V POD PIN_MH56 DDR4D_DQ24 Data [24] 1.2V POD PIN_LN60 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 60 1.2V POD PIN_MK45 DDR4D_DQ54 Data [54] 1.2V POD PIN_MD44 DDR4D_DQ55 Data [55] 1.2V POD PIN_MC41 DDR4D_DQ56 Data [56] 1.2V POD PIN_LR37 DDR4D_DQ57 Data [57] 1.2V POD PIN_LN42 DDR4D_DQ58 Data [58] 1.2V POD PIN_LN38 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 61 1.2V POD PIN_MD42 Data Bus Inversion DDR4D_DBI_n7 1.2V POD PIN_LR39 Data Bus Inversion DDR4D_DBI_n8 1.2V POD PIN_KF52 DDR4D_CS_n[0] Chip Select SSTL-12 PIN_LB44 DDR4D_CS_n[1] Chip Select SSTL-12 PIN_KW49 DDR4D_RESET_n Chip Reset 1.2 V PIN_LL45 MA27 www.terasic.com User Manual February 17, 2024...

  • Page 62: Qspf-Dd Ports

    25Gbps NRZ modulation or 8 pairs 50Gbps PAM4 and can support 400G ethernet. Furthermore, the QSFP-DD modules also can backward compatible with QSFP28 and QSFP+ optical transceivers. Figure 2-23 shows the connections between the QSFP-DD and Agilex FPGA. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 63 High Speed QSFPDDA_TX_p5 PIN_LA74 data of channel 5 Differential I/O Transmitter non-inverted High Speed QSFPDDA_TX_p6 PIN_KL77 data of channel 6 Differential I/O Transmitter non-inverted High Speed QSFPDDA_TX_p7 PIN_KH74 data of channel 7 Differential I/O MA27 www.terasic.com User Manual February 17, 2024...
  • Page 64 Differential I/O Receiver non-inverted data High Speed QSFPDDA_RX_p7 PIN_KL83 of channel 7 Differential I/O Receiver inverted data of High Speed QSFPDDA_RX_n0 PIN_ME76 channel 0 Differential I/O QSFPDDA_RX_n1 Receiver inverted data of High Speed PIN_LT76 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 65 Schematic Agilex Pin Description I/O Standard Signal Name Number Transmitter non-inverted High Speed QSFPDDB_TX_p0 PIN_JW77 data of channel 0 Differential I/O Transmitter non-inverted High Speed QSFPDDB_TX_p1 PIN_JT74 data of channel 1 Differential I/O MA27 www.terasic.com User Manual February 17, 2024...
  • Page 66 Differential I/O Receiver non-inverted data High Speed QSFPDDB_RX_p1 PIN_JW83 of channel 1 Differential I/O Receiver non-inverted data High Speed QSFPDDB_RX_p2 PIN_JT80 of channel 2 Differential I/O QSFPDDB_RX_p3 Receiver non-inverted data High Speed PIN_JG83 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 67 QSFPDDB_INTERRUPT_n Interrupt 1.2V PIN_LL57 QSFPDDB_MOD_PRS_n Module Present 1.2V PIN_KW57 QSFPDDB_MOD_SEL_n Module Select 1.2V PIN_LH56 QSFPDDB_RST_n Module Reset 1.2V PIN_KJ57 QSFPDDB_SCL 2-wire serial interface clock 1.2V PIN_LB58 QSFPDDB_SDA 2-wire serial interface data 1.2V PIN_LB56 MA27 www.terasic.com User Manual February 17, 2024...

  • Page 68: Pci Express

    PCIe lane. Please see the section 2.3 : Setup PCI Express Control DIP switch for detailed. Table 2-22 summarizes the PCI Express pin assignments of the signal names relative to the Agilex FPGA. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 69 Add-in card transmit bus Differential I/O HIGH Speed PIN_BP74 PCIE_TX_p6 Add-in card transmit bus Differential I/O HIGH Speed PIN_BE77 PCIE_TX_p7 Add-in card transmit bus Differential I/O PCIE_TX_p8 Add-in card transmit bus HIGH Speed PIN_BB74 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 70 Add-in card transmit bus Differential I/O HIGH Speed PIN_BH76 PCIE_TX_n7 Add-in card transmit bus Differential I/O HIGH Speed PIN_AW73 PCIE_TX_n8 Add-in card transmit bus Differential I/O HIGH Speed PIN_AR76 PCIE_TX_n9 Add-in card transmit bus Differential I/O MA27 www.terasic.com User Manual February 17, 2024...
  • Page 71 Add-in card receive bus Differential I/O HIGH Speed PIN_AJ80 PCIE_RX_p9 Add-in card receive bus Differential I/O HIGH Speed PIN_AC82 PCIE_RX_p10 Add-in card receive bus Differential I/O PCIE_RX_p11 Add-in card receive bus HIGH Speed PIN_V80 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 72 Add-in card receive bus Differential I/O HIGH Speed PIN_Y83 PCIE_RX_n10 Add-in card receive bus Differential I/O HIGH Speed PIN_T79 PCIE_RX_n11 Add-in card receive bus Differential I/O HIGH Speed PIN_M83 PCIE_RX_n12 Add-in card receive bus Differential I/O MA27 www.terasic.com User Manual February 17, 2024...

  • Page 73: Mcio Connector

    Agilex FPGA’s 16 R-tile transceiver channels for CXL or PCIe* interface applications.Users can use cable to connect the board to the host and establish CXL or PCIe* link. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 74 Figure 2-25 MCIO connectors on Mercury A2700 Accelerator Card Figure 2-26 MCIO connectors connection to FPGA Table 2-23 shows the FPGA dedicated clock input pin placement on the MCIO connectors. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 75 CXL transmit bus High Speed Differential I/O CXL_TX_n[2] PIN_FW22 CXL transmit bus High Speed Differential I/O CXL_TX_n[3] PIN_GJ16 CXL transmit bus High Speed Differential I/O CXL_TX_n[4] PIN_GM22 CXL transmit bus High Speed Differential I/O MA27 www.terasic.com User Manual February 17, 2024...
  • Page 76 CXL receive bus High Speed Differential I/O CXL_RX_p[13] PIN_KG1 CXL receive bus High Speed Differential I/O CXL_RX_p[14] PIN_KT8 CXL receive bus High Speed Differential I/O CXL_RX_p[15] PIN_KY1 CXL receive bus High Speed Differential I/O MA27 www.terasic.com User Manual February 17, 2024...

  • Page 77: Usb To Uart

    2.11 USB to UART The board provides two UART functions (See Figure 2-27). One of them is connected to HPS fabric in the Agilex FPGA, allowing host to communicate and debug with the MA27 www.terasic.com User Manual February 17, 2024...
  • Page 78 HPS, CP2105 chip, and the Micro USB connector. Table 2-24 lists the pin assignment of UART interface connected to the HPS. Figure 2-28 Connections between the HPS of Apollo Agilex and FT232R Chip MA27 www.terasic.com User Manual February 17, 2024...
  • Page 79 (such as a fan failure condition), the FPGA power will be cut to protect the board. See chapter 3 for details. Terasic also provide a “board information IP” that allow user can place it in the Agilex FPGA to read these board status. Please refer to the section 2.5 of the demonstration manual.

  • Page 80: Usb 2.0 Otg Phy

    PIN_CA27 HPS USB_DATA[4] 1.8V HPS_USB_DATA[5] PIN_AE3 HPS USB_DATA[5] 1.8V HPS_USB_DATA[6] PIN_BV28 HPS USB_DATA[6] 1.8V HPS_USB_DATA[7] PIN_AB1 HPS USB_DATA[7] 1.8V HPS_USB_DIR PIN_BJ33 Direction of the Data Bus 1.8V HPS_USB_NXT PIN_AB14 Throttle the Data 1.8V MA27 www.terasic.com User Manual February 17, 2024...

  • Page 81: Micro Sd Card Socket

    HPS SD Data[2] 1.8-V PIN_W26 HPS_SD_DATA[3] HPS SD Data[3] 2.14 Gigabit Ethernet The board supports Gigabit Ethernet transfer by an external Micrel KSZ9031RN PHY chip and HPS Ethernet MAC function. The KSZ9031RN chip with integrated MA27 www.terasic.com User Manual February 17, 2024...
  • Page 82 LEDY Link off 1000 Link / No Activity Toggle Blinking 1000 Link / Activity (RX, TX) 100 Link / No Activity Toggle Blinking 100 Link / Activity (RX, TX) 10 Link/ No Activity MA27 www.terasic.com User Manual February 17, 2024...

  • Page 83: System Status Interface

    2.15 System Status Interface As shown in Figure 2-33, the Mercury A2700 Accelerator Card provides several sensors to monitor the status of the board, such as FPGA temperature, board power monitor, and fan speed status. These interfaces are connected to the System MAX10 FPGA on the board.
  • Page 84 Finally, the board status also can be read on the Agilex FPGA side via the SPI interface connected to the System MAX10 FPGA. Terasic had provided a “board information IP” that allow user can place it in the FPGA to read these board status.

  • Page 85: Qspi-Flash Programming

    In this chapter, we will introduce how to correctly set the FPGA to work in AVSTx8 mode, how to program bit stream files into the QSPI Flash, and how to switch the image file to be loaded. MA27 www.terasic.com User Manual February 17, 2024...

  • Page 86: Fpga Configure Operation

    (The board ships with two images in the 2Gbit QSPI flash). Set the FPGA configuration mode to AVSTx8 mode by setting SW4 and SW5 MSEL[2:0] as 110 as shown in Figure 3-2. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 87 When the configuration is completed, the green Configure Done LED will light. If there is an error, the red Configure Error LED will light (See Figure 3-4). Figure 3-2 Position of the MSEL[2:0] switch MA27 www.terasic.com User Manual February 17, 2024...

  • Page 88: Qspi Flash Memory Map

    QSPI Flash Memory Map The MA27 has one 2-Gbit QSPI flash device for non-volatile storage of the FPGA configuration data for AVTSx8 Mode. Only the System MAX10 FPGA can access this Flash device. MA27 www.terasic.com User Manual February 17, 2024...

  • Page 89: Programming Bit Stream File Into Qspi Flash

    The QSPI Flash of the MA27 board can only be programmed from the Host PC through the JTAG interface. The QSPI Flash is connected to the system MAX10 FPGA on the board. Before program the QSPI flash, users must set MSEL[2:0]=110 for AVSTx8 MA27 www.terasic.com User Manual February 17, 2024...
  • Page 90 JTAG interface and program the .pof file into QSPI Flash. In order to help users easily and quickly program the QSPI Flash on the board, Terasic provides some batch files so that users can quickly complete the operations for the QSPI Flash such as erasing and programming.
  • Page 91 QSPI Flash.  Program .pof inot QSPI Flash Executing the AVSTx8_pogram.bat will program the AVSTx8.pof file from Host to QSPI Flash via System MAX10 FPGA on MA27 board (please make sure the MA27 www.terasic.com User Manual February 17, 2024...

  • Page 92: Restore Factory Settings

    FACTORY_LOAD dip in SW4 to the ‘1’ position. Power on the FPGA Board, and the Configure Done LED should light up. Batch file sof_2_pof.bat merges the Factory and User .sof and PFL option bit into a MA27 www.terasic.com User Manual February 17, 2024...
  • Page 93 AVTSx8.pof file. Batch file AVSTx8_program.bat calls Quartus Programmer to program the QSPI-Flash with the generated AVST8x.pof. The factory.sof files generated by LED_BLINK project, and the user.sof files generated by PCIe_DDR4 project. MA27 www.terasic.com User Manual February 17, 2024...

  • Page 94: Chapter 4 Dashboard Gui

    To use the dashboard system, users need to install the USB to UART driver on the host first, so that user can establish a connection with the Mercury A2700 Accelerator Card. This section will describe how to install USB to UART driver on the windows OS host.
  • Page 95 Accelerator Card system CD and copy it to the Host.  Connection Setting Connect the Micro USB connector of the Mercury A2700 Accelerator Card to the Host USB port through Micro USB cable. Figure 4-2 Connection setup for using dashboard system Connect power to the Mercury A2700 Accelerator Card.
  • Page 96 Figure 4-3 Uninstalled USB to UART device Copy the device driver (System CD\Tool\dashboard_gui\Driver) to the Host and install it, as shown in Figure 4-4. Please note that the COM Port number is different in different Host. MA27 www.terasic.com User Manual February 17, 2024...

  • Page 97: Run Dashboard Gui

    Users can find it from the path: Tool\dashboard_gui\Dashboard.exe in the Mercury A2700 Accelerator Card system CD and copy it to the Host. Execute the Dashboard.exe, a window will show as Figure 4-6. It will describe the detail functions as below. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 98 4-7, there is a Start button at the bottom-left of the GUI window. Click it to run the program (Start will change to Stop), it will show the Mercury A2700 Accelerator Card status. Users can press Stop button to stop the status data transmission and display.
  • Page 99  FPGA Status: As shown in Figure 4-8, it will show the status LED number on the Mercury A2700 Accelerator Card. The definitions of these indicator LEDs are as follows:  FPGA_SD_LED When this status is shown in green on the GUI, it means that the FPGA temperature or the board temperature exceeds 95 degrees or the power consumption exceeds 180W.
  • Page 100  FPGA/Board/Transceiver Temperature: The Dashboard GUI will real-time show the Mercury A2700 Accelerator Card’s ambient temperature (Board,Board2 and Board3 data in the GUI) and FPGA and Power transceiver temperature. Users can get the board’s temperature status in time. The information will be refreshed...
  • Page 101 Figure 4-9 Temperature section Figure 4-10 Location of the board’s ambient temperature MA27 www.terasic.com User Manual February 17, 2024...
  • Page 102  Fan RPM: It displays the real-time speed of the two fans (Fan and Fan2 in the GUI) on the Mercury A2700 Accelerator Card, as shown in Figure 4-11. Figure 4-11 FAN RPM section  12V/Core Power monitor: It displays the real-time 12V/Core Power (0.8V~0.85V) voltage and consumption current on the Mercury A2700 Accelerator Card.
  • Page 103 Figure 4-12 Select “12V Power” MA27 www.terasic.com User Manual February 17, 2024...
  • Page 104 Sampling Speed: It can change interval time that the Dashboard GUI sample the board status. Users can adjust it to 1s/10s/1min/Full Speed (0.1s) to sample the board status, as shown in Figure 4-14 Figure 4-15. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 105 Note that to active these functions, you will need to stop obtaining the board status (i.e. Don’t Press “Start” button or Press "Stop" button) in the GUI. Detailed introductions of these functions are described in below. MA27 www.terasic.com User Manual February 17, 2024...
  • Page 106 “Auto shutdown status” because the FPGA temperature is too high or the fan speed is abnormal.  Board Information: Click the “Board Information” to get the current MAX 10 FPGA software version and the Mercury A2700 Accelerator Card version, as shown in Figure 4-17.
  • Page 107 Log File: Click the Export in the File page to save the board temperature, fan speed and voltage data in .csv format document, as shown in Figure 4-18 Figure 4-19. Figure 4-18 Export the log file Figure 4-19 Export the log file in .csv format MA27 www.terasic.com User Manual February 17, 2024...

  • Page 108: Chapter 5 Additional Information

    Here are the addresses where you can get help if you encounter problems:  Terasic Technologies No.80, Fenggong Rd., Hukou Township, Hsinchu County 303035. Taiwan Email: support@terasic.com Web: www.terasic.com Mercury A2700 Accelerator Card Web: A7SK.terasic.com  Revision History Date Version Changes 2023.08 First publication 2023.11...

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