Mcio Connector - Terasic Mercury A2700 User Manual

PCIE_RX_n13
PCIE_RX_n14
PCIE_RX_n15
PCIE_CLKREQ_n
PCIE_REFCLK_14C_p[0]
PCIE_REFCLK_14C_p[1]
PCIE_PERST_n
PCIE_WAKE_n

2.10 MCIO Connector

This board provides two 74-pin MCIO connectors (See
that can be used to connect to Agilex FPGA's 16 R-tile transceiver channels for CXL or
PCIe* interface applications.Users can use cable to connect the board to the host and
establish CXL or PCIe* link.
MA27
User Manual
Add-in card receive bus
Add-in card receive bus
Add-in card receive bus
Request the reference clock
Motherboard reference clock
Motherboard reference clock
Reset
Active-low signal that is used to
return the PCIe interafce to an
active state when in a low-power
state
73
HIGH Speed PIN_G79
Differential I/O
HIGH Speed PIN_P76
Differential I/O
HIGH Speed PIN_E76
Differential I/O
1.2V PIN_B49
HCSL PIN_DR68
HCSL PIN_CU68
1.8V PIN_CD58
PIN_W52
1.2V
Figure 2-25 and Figure
www.terasic.com
February 17,
2-26)
2024