Usb Epm Interrupt Enable Registers - Epson S1C31W74 Technical Manual

22 USB 2.0 FS DEVICE CONTROLLER (USB, USBMISC)
Bits 7–6 Reserved
Bit 5 INACKIE
Bit 4 OUTACKIE
Bit 3 INNAKIE
Bit 2 OUTNAKIE
Bit 1 INERRIE
Bit 0 OUTERRIE
These bits enable EP0 interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
USBEP0INTE.INACKIE bit:
USBEP0INTE.OUTACKIE bit: EP0 ACK transmission interrupt
USBEP0INTE.INNAKIE bit:
USBEP0INTE.OUTNAKIE bit: EP0 NAK transmission interrupt
USBEP0INTE.INERRIE bit:
USBEP0INTE.OUTERRIE bit: EP0 STALL transmission interrupt
When an interrupt flag in the USBEP0INTF register that is enabled using this register is set, the USB-
MAININTF.EP0IF bit is set. To generate an EP0 interrupt to the CPU, the USBMAININTE.EP0IE bit
must be set to 1 in addition to this register.

USB EPm Interrupt Enable Registers

Register name Bit
USBEPmINTE 7
6
5
4
3
2
1
0
Bit 7 Reserved
Bit 6 OUTSHACKIE
Bit 5 INACKIE
Bit 4 OUTACKIE
Bit 3 INNAKIE
Bit 2 OUTNAKIE
Bit 1 INERRIE
Bit 0 OUTERRIE
These bits enable EPm interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
USBEPmINTE.OUTSHACKIE bit: EPm short packet reception interrupt
USBEPmINTE.INACKIE bit:
USBEPmINTE.OUTACKIE bit:
USBEPmINTE.INNAKIE bit:
USBEPmINTE.OUTNAKIE bit:
USBEPmINTE.INERRIE bit:
USBEPmINTE.OUTERRIE bit:
22-40
EP0 ACK reception interrupt
EP0 NAK reception interrupt
EP0 STALL reception interrupt
Bit name Initial
– 0
OUTSHACKIE 0
INACKIE 0
OUTACKIE 0
INNAKIE 0
OUTNAKIE 0
INERRIE 0
OUTERRIE 0
EPm ACK reception interrupt
EPm ACK transmission interrupt
EPm NAK reception interrupt
EPm NAK transmission interrupt
EPm STALL reception interrupt
EPm STALL transmission interrupt
Seiko Epson Corporation
Reset R/W
– R –
H0/S0 R/W
H0/S0 R/W
H0/S0 R/W
H0/S0 R/W
H0/S0 R/W
H0/S0 R/W
H0/S0 R/W
S1C31W74 TECHNICAL MANUAL
Remarks
(Rev. 1.1)