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16 I
2
C (I2C)
Data sending operations
START condition detection and slave address check
While the I2C_nCTL.MODEN bit = 1 and the I2C_nCTL.MST bit = 0 (slave mode), the I2C Ch.n monitors
the I
C bus. When the I2C Ch.n detects a START condition, it starts receiving of the slave address sent from
2
the master. If the received address is matched with the own address set to the I2C_nOADR.OADR[6:0] bits
(when the I2C_nMOD.OADR10 bit = 0 (7-bit address mode)) or the I2C_nOADR.OADR[9:0] bits (when the
I2C_nMOD.OADR10 bit = 1 (10-bit address mode)), the I2C_nINTF.STARTIF bit and the I2C_nINTF.BSY
bit are both set to 1. The I2C Ch.n sets the I2C_nINTF.TR bit to the R/W bit value in the received address. If
this value is 1, the I2C Ch.n sets the I2C_nINTF.TBEIF bit to 1 and starts data sending operations.
Sending the first data byte
After the valid slave address has been received, the I2C Ch.n pulls down SCL to low and enters standby
state until data is written to the I2C_nTXD register. This puts the I
external master into standby state. When transmit data is written to the I2C_nTXD register, the I2C Ch.n
clears the I2C_nINTF.TBEIF bit and sends an ACK to the master. The transmit data written in the I2C_
nTXD register is automatically transferred to the shift register and the I2C_nINTF.TBEIF bit is set to 1.
The data bits in the shift register are output in sequence to the I
Sending subsequent data
If the I2C_nINTF.TBEIF bit = 1, subsequent transmit data can be written during data transmission. If the
I2C_nINTF.TBEIF bit is still set to 1 when the data transmission from the shift register has completed, the
I2C Ch.n pulls down SCL to low (sets the I
to the I2C_nTXD register.
If the next transmit data already exists in the I2C_nTXD register or data has been written after the above,
the I2C Ch.n sends the subsequent eight-bit data when an ACK from the external master is received. At the
same time, the I2C_nINTF.BYTEENDIF bit is set to 1. If a NACK is received, the I2C_nINTF.NACKIF bit
is set to 1 without sending data.
STOP/repeated START condition detection
While the I2C_nCTL.MST bit = 0 (slave mode) and the I2C_nINTF.BSY = 1, the I2C Ch.n monitors the I
bus. When the I2C Ch.n detects a STOP condition, it terminates data sending operations. At this time, the
I2C_nINTF.BSY bit is cleared to 0 and the I2C_nINTF.STOPIF bit is set to 1. Also when the I2C Ch.n detects
a repeated START condition, it terminates data sending operations. In this case, the I2C_nINTF.STARTIF bit
is set to 1.
Clock stretching by I2C
Data 1
I
2
C bus
S
Saddr/R
A
BSY = 1
TR = 1
STARTIF = 1
TBEIF = 1
Software bit operations
Operations by the external master
S: START condition, Sr: Repeated START condition, P: STOP condition,
A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0),
Data n: 8-bit data
Figure 16.4.5.1 Example of Data Sending Operations in Slave Mode
16-12
2
→
→
TXD[7:0]
Data 2
TXD[7:0] Data 3
Data 1
A
Data 2
TBEIF = 1
TBEIF = 1
BYTEENDIF = 1
Hardware bit operations
Operations by I2C (slave mode)
Seiko Epson Corporation
C bus into clock stretching state and the
2
C bus.
2
C bus into clock stretching state) until transmit data is written
→
TXD[7:0]
Data N
A
Data 3
A
TBEIF = 1
NACKIF = 1
BYTEENDIF = 1
BYTEENDIF = 1
→
TXD[7:0]
P
BSY = 0
STOPIF = 1
Sr
Saddr/R
Data transmission continued
BSY = 1
STARTIF = 1
TBEIF = 1
Sr
Saddr/W
Data reception starts
TR = 0
BSY = 1
STARTIF = 1
S1C31W74 TECHNICAL MANUAL
C
2
(Rev. 1.1)
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