Terminating Data Transfer In Slave Mode; Interrupts - Epson S1C31W74 Technical Manual

Data transmission
Read the QSPI_nINTF.TBEIF bit
QSPI_nINTF.TBEIF = 1 ?
YES
Write transmit data to
the QSPI_nTXD register
Transmit data remained?
NO
End

15.5.10 Terminating Data Transfer in Slave Mode

A procedure to terminate data transfer in slave mode is shown below.
1. Wait for an end-of-transmission interrupt (QSPI_nINTF.TENDIF bit = 1). Or determine end of transfer via the
received data.
2. Set the QSPI_nCTL.MODEN bit to 0 to disable the QSPI Ch.n operations.

15.6 Interrupts

The QSPI has a function to generate the interrupts shown in Table 15.6.1.
Interrupt
End of transmission QSPI_nINTF.TENDIF When the QSPI_nINTF.TBEIF bit = 1 after data
Receive buffer full QSPI_nINTF.RBFIF
Transmit buffer empty QSPI_nINTF.TBEIF
Overrun error QSPI_nINTF.OEIF
The QSPI provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the
CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more
information on interrupt control, refer to the "Interrupt" chapter.
The QSPI_nINTF register also contains the BSY and MMABSY bits that indicate the QSPI operating status in reg-
ister access and memory mapped access modes, respectively. Figure 15.6.1 shows the QSPI_nINTF.BSY, QSPI_
nINTF.MMABSY and QSPI_nINTF.TENDIF bit set timings.
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
NO
YES
Wait for an interrupt request
(QSPI_nINTF.TBEIF = 1)
Figure 15.5.9.2 Data Transfer Flowcharts in Slave Mode
Table 15.6.1 QSPI Interrupt Function
Interrupt flag
of the specified bit length (defined by the QSPI_
nMOD.CHLN[3:0] bits) has been sent
When data of the specified bit length is received
and the received data is transferred from the shift
register to the received data buffer
When transmit data written to the transmit data
buffer is transferred to the shift register
When the receive data buffer is full (when the re-
ceived data has not been read) at the point that
receiving data to the shift register has completed
Seiko Epson Corporation
15 QUAD SYNCHRONOUS SERIAL INTERFACE (QSPI)
Wait for an interrupt request
(QSPI_nINTF.RBFIF = 1)
Read receive data from
the QSPI_nRXD register
Receive data remained?
Set condition
Data reception
NO
End
Clear condition
Writing 1
Reading of the
QSPI_nRXD
register
Writing to the
QSPI_nTXD register
Writing 1
15-27
YES