Dma Transfer Requests; Control Registers; Usb Control Register - Epson S1C31W74 Technical Manual

22 USB 2.0 FS DEVICE CONTROLLER (USB, USBMISC)
Interrupt request
to CPU core
The USB controller provides interrupt enable bits corresponding to the interrupt flags in the USBMAININTF regis-
ter. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the
interrupt enable bit, is set.
The interrupt flags other than above also have a corresponding interrupt enable bit. These interrupt flags do not
cause an interrupt request to be output directly to the CPU. When an interrupt flag for the interrupt enabled is set, the
higher-level interrupt flag, which is marked with *, is set simultaneously.
For more information on interrupt control, refer to the "Interrupt" chapter.

22.7 DMA Transfer Requests

The USB controller has a function to generate DMA transfer requests from the causes shown in Table 22.7.1.
Cause to request DMA
transfer
Write endpoint status USBREMSPCCNT register status flag
(internal signal)
Read endpoint status USBREMDATCNT register status flag
(internal signal)
The USB controller provides DMA transfer request enable bits corresponding to each DMA transfer request flag
shown above for the number of DMA channels. A DMA transfer request is sent to the pertinent channel of the DMA
controller only when the DMA transfer request flag, of which DMA transfer has been enabled by the DMA transfer
request enable bit, is set. For more information on the DMA control, refer to the "DMA Controller" chapter.

22.8 Control Registers

Note: Do not perform 32-bit access to read and write from/to the USB registers as it may cause mal-
function.

USB Control Register

Register name Bit
USBCTL 7
6
5
4
3
2–1 –
0
22-22
USBMAININTF.SIEIF *
USBMAININTE.SIEIE
USBMAININTF.GPEPIF *
USBMAININTE.GPEPIE
USBMAININTF.EP0IF *
USBMAININTE.EP0IE
USBMAININTF.EP0SETIF
USBMAININTE.EP0SETIE
Figure 22.6.1 USB Interrupt System
Table 22.7.1 DMA Transfer Request Causes of USB Controller
DMA transfer request flag
Bit name Initial
BUSDETDIS
AUTONEGOEN
NONJDETEN
JDETEN
WAKEUP
0x0
USBEN
Seiko Epson Corporation
USBSIEINTF.xxxIF
USBSIEINTE.xxxIE
USBSIEINTF.xxxIF
USBSIEINTE.xxxIE
USBGPEPINTF.EPAIF *
USBGPEPINTF.EPAIE
USBGPEPINTF.EPxIF *
USBGPEPINTF.EPxIE
USBE0INTF.xxxIF
USBE0INTE.xxxIE
USBE0INTF.xxxIF
USBE0INTE.xxxIE
DMA transfer request issuing timing
When an available space is generated in the FIFO
selected by the USBWRFIFOSEL.EPmWR bit
When valid data is loaded into the FIFO selected by
the USBRDFIFOSEL.EPmRD bit.
Reset R/W
0 H0/S0 R/W –
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
– R
0 H0/S0 R/W
USBEPAINTF.xxxIF
USBEPAINTF.xxxIE
USBEPAINTF.xxxIF
USBEPAINTF.xxxIE
USBEPxINTF.xxxIF
USBEPxINTF.xxxIE
USBEPxINTF.xxxIF
USBEPxINTF.xxxIE
Remarks
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)