Interrupt; Control Registers; Lcd32B Clock Control Register - Epson S1C31W74 Technical Manual

20 LCD DRIVER (LCD32B)

20.7 Interrupt

The LCD32B has a function to generate the interrupt shown in Table 20.7.1.
Interrupt
Frame LCD32BINTF.FRMIF Frame switching
The LCD32B provides an interrupt enable bit corresponding to the interrupt flag. An interrupt request is sent to the
CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more
information on interrupt control, refer to the "Interrupt" chapter.
0
LFRO
COM0
COMx

20.8 Control Registers

LCD32B Clock Control Register

Register name Bit
LCD32BCLK 15–9 –
8
7
6–4 CLKDIV[2:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the LCD32B operating clock is supplied during debugging or not.
1 (R/W): Clock supplied during debugging
0 (R/W): No clock supplied during debugging
Bit 7 Reserved
Bits 6–4 CLKDIV[2:0]
These bits select the division ratio of the LCD32B operating clock.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of the LCD32B.
20-26
Table 20.7.1 LCD32B Interrupt Function
Interrupt flag
1 frame
x - 1 0
Figure 20.7.1 Frame Interrupt Timings (1/x duty, 1/5 bias)
Bit name Initial
0x00
DBRUN 1
– 0
0x0
0x0
0x0
Seiko Epson Corporation
Set condition
Writing 1
Reset R/W
– R –
H0 R/W
– R
H0 R/W
– R
H0 R/W
Clear condition
x - 1
Remarks
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
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C5
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C4
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C3
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C2
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C1
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SS
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C5
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C4
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C3
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C2
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C1
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SS