Clock Supply During Debugging; Operations; Svd2 Control - Epson S1C31W74 Technical Manual

11.3.3 Clock Supply During Debugging

The CLK_SVD2_n supply during debugging should be controlled using the SVD2_nCLK.DBRUN bit.
The CLK_SVD2_n supply to SVD2 Ch.n is suspended when the CPU enters debug state if the SVD2_nCLK.DB-
RUN bit = 0. After the CPU returns to normal operation, the CLK_SVD2_n supply resumes. Although SVD2 Ch.n
stops operating when the CLK_SVD2_n supply is suspended, the registers retain the status before the debug state
was entered. If the SVD2_nCLK.DBRUN bit = 1, the CLK_SVD2_n supply is not suspended and SVD2 Ch.n will
keep operating in a debug state.

11.4 Operations

11.4.1 SVD2 Control

Starting detection
SVD2 Ch.n should be initialized and activated with the procedure listed below.
1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)
2. Configure the operating clock using the SVD2_nCLK.CLKSRC[1:0] and SVD2_nCLK.CLKDIV[2:0] bits.
3. Set the following SVD2_nCTL register bits:
- SVD2_nCTL.VDSEL bit
- SVD2_nCTL.SVDF bit
- SVD2_nCTL.SVDSC[1:0] bits
- SVD2_nCTL.SVDC[4:0] bits
- SVD2_nCTL.SVDRE[3:0] bits
- SVD2_nCTL.SVDMD[1:0] bits
4. Set the following bits when using the interrupt:
- Write 1 to the SVD2_nINTF.SVDIF bit.
- Set the SVD2_nINTE.SVDIE bit to 1.
5. Set the SVD2_nCTL.MODEN bit to 1.
6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits.
Terminating detection
Follow the procedure shown below to stop SVD2 Ch.n operation.
1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)
2. Write 0 to the SVD2_nCTL.MODEN bit.
3. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits.
Reading detection results
The following four detection results can be obtained by reading the SVD2_nINTF.SVDDT bit:
SVD2_nCTL.SVDF bit SVD2_nINTF.SVDDT bit
0
0
1
1
Before reading the SVD2_nINTF.SVDDT bit, wait for at least SVD circuit enable response time after 1 is writ-
ten to the SVD2_nCTL.MODEN bit (refer to "Supply Voltage Detector Characteristics, SVD circuit enable
response time t " in the "Electrical Characteristics" chapter).
SVDEN
After the SVD2_nCTL.SVDC[4:0] bits setting value is altered to change the SVD detection voltage V
the SVD2_nCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVD2_nINTF.
SVDDT bit (refer to "Supply Voltage Detector Characteristics, SVD circuit response time t
Characteristics" chapter).
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
(Select detection voltage (V
(Select detection mode (voltage drop or rise))
(Set power supply voltage drop/rise detection counter)
(Set SVD detection voltage V
(Select reset/interrupt mode)
(Set intermittent operation mode)
(Clear SVD2 Ch.n interrupt flag)
(Enable SVD2 Ch.n interrupt)
(Enable SVD2 Ch.n detection)
(Disable SVD2 Ch.n detection)
Table 11.4.1.1 Detection Results
0 Power supply voltage (V
1 Power supply voltage (V
0 Power supply voltage (V
1 Power supply voltage (V
Seiko Epson Corporation
11 SUPPLY VOLTAGE DETECTOR (SVD2)
or EXSVDn))
DD
)
SVD
(Set system protection)
(Set system protection)
Detection results
or EXSVDn) ≥ SVD detection voltage V
DD
or EXSVDn) < SVD detection voltage V
DD
or EXSVDn) < SVD detection voltage V
DD
or EXSVDn) ≥ SVD detection voltage V
DD
SVD
SVD
SVD
SVD
SVD
when
SVD
" in the "Electrical
11-3