Terminating Memory Mapped Access Operations; Terminating Data Transfer In Master Mode - Epson S1C31W74 Technical Manual

Item
End pointer Transfer source
Transfer destination Memory area start address from which the read data are stored
Control data dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl
The following shows an example of the control procedure including the DMA controller operations:
1. Configure the primary data structure for the DMA channel (Ch.x) as shown in Table 15.5.6.1.
2. Enable the DMA channel using the DMA controller register.
3. Clear the channel request mask for the DMA channel using the DMA controller register.
4. Clear the DMA transfer completion interrupt flag using the DMA controller register.
5. Enable the DMA transfer completion interrupt of the DMA channel using the DMA controller register.
6. Clear pending DMA interrupts in the CPU.
7. Enable pending DMA interrupts in the CPU.
8. Enable the QSPI to issue DMA transfer requests to the DMA channel using the QSPI_nFRLDMAEN.
FRLDMAENx bit.
9. Issue a software DMA transfer request to the DMA channel by setting the DMA controller register. This op-
eration is required to kickstart the first data fetching.
10. Wait for a DMA interrupt.
11. Disable DMA requests to be sent to the DMA channel using the QSPI_nFRLDMAEN.FRLDMAENx bit.
12. Set the channel request masks for the DMA channel using the DMA controller register.
13. Disable the DMA channels using the DMA controller register.

15.5.7 Terminating Memory Mapped Access Operations

A procedure to terminate memory mapped access operations is shown below.
1. Write 0 to the QSPI_nMMACFG2.MMAEN bit. (Disable memory mapped access mode)
The slave select signal is negated. Note that the slave signal control via software is disabled by the state ma-
chine in memory mapped access mode.
2. Wait until the QSPI_nINTF.MMABSY bit is set to 0 (memory mapped access operation not busy).

15.5.8 Terminating Data Transfer in Master Mode

A procedure to terminate data transfer in master mode is shown below.
1. Wait for an end-of-transmission interrupt (QSPI_nINTF.TENDIF bit = 1).
2. Set the QSPI_nCTL.MODEN bit to 0 to disable the QSPI Ch.n operations.
3. Stop the 16-bit timer to disable the clock supply to QSPI Ch.n.
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
Table 15.5.6.1 DMA Data Structure Configuration Example
(for 32-bit Sequential Read in Memory Mapped Access Mode)
External Flash memory transfer start address
0x2 (+4)
0x2 (word)
0x2 (+4)
0x2 (word)
0x0 (arbitrated for every transfer)
Number of receive data
0x1 (basic transfer)
Seiko Epson Corporation
15 QUAD SYNCHRONOUS SERIAL INTERFACE (QSPI)
Setting example
15-25