Qspi Ch.n Transmit Data Register; Qspi Ch.n Receive Data Register; Qspi Ch.n Interrupt Flag Register - Epson S1C31W74 Technical Manual

15 QUAD SYNCHRONOUS SERIAL INTERFACE (QSPI)

QSPI Ch.n Transmit Data Register

Register name Bit
QSPI_nTXD 15–0 TXD[15:0]
Bits 15–0 TXD[15:0]
Data can be written to the transmit data buffer through these bits. Writing to these bits starts data
transfer. Transmit data can be written when the QSPI_nINTF.TBEIF bit = 1 regardless of whether data
is being output from the QSDIOn pins or not.
Note that the upper data bits that exceed the data bit length configured by the QSPI_nMOD.
CHLN[3:0] bits will not be output from the QSDIOn pin.
Note: Be sure to avoid writing to the QSPI_nTXD register when the QSPI_nINTF.TBEIF bit = 0. Other-
wise, transfer data cannot be guaranteed.

QSPI Ch.n Receive Data Register

Register name Bit
QSPI_nRXD 15–0 RXD[15:0]
Bits 15–0 RXD[15:0]
The receive data buffer can be read through these bits. Received data can be read when the QSPI_
nINTF.RBFIF bit = 1 regardless of whether data is being input from the QSDIOn pin or not.
Note that the upper bits that exceed the data bit length configured by the QSPI_nMOD.CHLN[3:0]
bits become 0.

QSPI Ch.n Interrupt Flag Register

Register name Bit
QSPI_nINTF 15–8 –
7
6
5–4 –
3
2
1
0
Bits 15–8 Reserved
Bit 7 BSY
This bit indicates the QSPI operating status.
1 (R): Transmit/receive busy
0 (R): Idle
Bit 6 MMABSY
This bit indicates the QSPI memory mapped access operating status.
1 (R): Memory mapped access state machine busy
0 (R): Idle
Bits 5–4 Reserved
15-32
Bit name Initial
0x0000
Bit name Initial
0x0000
Bit name Initial
0x00
BSY 0
MMABSY 0
0x0
OEIF 0
TENDIF 0
RBFIF 0
TBEIF 1
Seiko Epson Corporation
Reset R/W
H0 R/W –
Reset R/W
H0 R –
Reset R/W
– R –
H0 R
H0 R
– R
H0/S0 R/W Cleared by writing 1.
H0/S0 R/W
H0/S0 R Cleared by reading the
QSPI_nRXD register.
H0/S0 R Cleared by writing to the
QSPI_nTXD register.
S1C31W74 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 1.1)