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Peripheral circuit
UART (UART2) Ch.1
16-bit timer (T16) Ch.2
Quad synchronous serial
interface (QSPI) Ch.0
I
C (I2C) Ch.1
2
Sound generator (SNDA)
IR remote controller (REMC2) 0x4000 0720 REMC2CLK
LCD driver (LCD32B)
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
Address
0x4000 060c UART2_1INTF
0x4000 060e UART2_1INTE
0x4000 0610 UART2_1
TBEDMAEN
0x4000 0612 UART2_1
RB1FDMAEN
0x4000 0680 T16_2CLK
0x4000 0682 T16_2MOD
0x4000 0684 T16_2CTL
0x4000 0686 T16_2TR
0x4000 0688 T16_2TC
0x4000 068a T16_2INTF
0x4000 068c T16_2INTE
0x4000 0690 QSPI_0MOD
0x4000 0692 QSPI_0CTL
0x4000 0694 QSPI_0TXD
0x4000 0696 QSPI_0RXD
0x4000 0698 QSPI_0INTF
0x4000 069a QSPI_0INTE
0x4000 069c QSPI_0TBEDMAEN QSPI Ch.0 Transmit Buffer Empty DMA Request Enable
0x4000 069e QSPI_0RBFDMAEN QSPI Ch.0 Receive Buffer Full DMA Request Enable
0x4000 06a0 QSPI_0FRLDMAEN
0x4000 06a2 QSPI_0MMACFG1
0x4000 06a4 QSPI_0RMADRH
0x4000 06a6 QSPI_0MMACFG2
0x4000 06a8 QSPI_0nMB
0x4000 06c0 I2C_1CLK
0x4000 06c2 I2C_1MOD
0x4000 06c4 I2C_1BR
0x4000 06c8 I2C_1OADR
0x4000 06ca I2C_1CTL
0x4000 06cc I2C_1TXD
0x4000 06ce I2C_1RXD
0x4000 06d0 I2C_1INTF
0x4000 06d2 I2C_1INTE
0x4000 06d4 I2C_1TBEDMAEN
0x4000 06d6 I2C_1RBFDMAEN
0x4000 0700 SNDACLK
0x4000 0702 SNDASEL
0x4000 0704 SNDACTL
0x4000 0706 SNDADAT
0x4000 0708 SNDAINTF
0x4000 070a SNDAINTE
0x4000 070c SNDAEMDMAEN
0x4000 0722 REMC2DBCTL
0x4000 0724 REMC2DBCNT
0x4000 0726 REMC2APLEN
0x4000 0728 REMC2DBLEN
0x4000 072a REMC2INTF
0x4000 072c REMC2INTE
0x4000 0730 REMC2CARR
0x4000 0732 REMC2CCTL
0x4000 0800 LCD32BCLK
0x4000 0802 LCD32BCTL
0x4000 0804 LCD32BTIM1
0x4000 0806 LCD32BTIM2
0x4000 0808 LCD32BPWR
Seiko Epson Corporation
Register name
UART2 Ch.1 Status and Interrupt Flag Register
UART2 Ch.1 Interrupt Enable Register
UART2 Ch.1 Transmit Buffer Empty DMA Request
Enable Register
UART2 Ch.1 Receive Buffer One Byte Full DMA
Request Enable Register
T16 Ch.2 Clock Control Register
T16 Ch.2 Mode Register
T16 Ch.2 Control Register
T16 Ch.2 Reload Data Register
T16 Ch.2 Counter Data Register
T16 Ch.2 Interrupt Flag Register
T16 Ch.2 Interrupt Enable Register
QSPI Ch.0 Mode Register
QSPI Ch.0 Control Register
QSPI Ch.0 Transmit Data Register
QSPI Ch.0 Receive Data Register
QSPI Ch.0 Interrupt Flag Register
QSPI Ch.0 Interrupt Enable Register
Register
Register
QSPI Ch.0 FIFO Data Ready DMA Request Enable
Register
QSPI Ch.0 Memory Mapped Access Configuration
Register 1
QSPI Ch.0 Remapping Start Address High Register
QSPI Ch.0 Memory Mapped Access Configuration
Register 2
QSPI Ch.0 Mode Byte Register
I2C Ch.1 Clock Control Register
I2C Ch.1 Mode Register
I2C Ch.1 Baud-Rate Register
I2C Ch.1 Own Address Register
I2C Ch.1 Control Register
I2C Ch.1 Transmit Data Register
I2C Ch.1 Receive Data Register
I2C Ch.1 Status and Interrupt Flag Register
I2C Ch.1 Interrupt Enable Register
I2C Ch.1 Transmit Buffer Empty DMA Request Enable
Register
I2C Ch.1 Receive Buffer Full DMA Request Enable
Register
SNDA Clock Control Register
SNDA Select Register
SNDA Control Register
SNDA Data Register
SNDA Interrupt Flag Register
SNDA Interrupt Enable Register
SNDA Sound Buffer Empty DMA Request Enable
Register
REMC2 Clock Control Register
REMC2 Data Bit Counter Control Register
REMC2 Data Bit Counter Register
REMC2 Data Bit Active Pulse Length Register
REMC2 Data Bit Length Register
REMC2 Status and Interrupt Flag Register
REMC2 Interrupt Enable Register
REMC2 Carrier Waveform Register
REMC2 Carrier Modulation Control Register
LCD32B Clock Control Register
LCD32B Control Register
LCD32B Timing Control Register 1
LCD32B Timing Control Register 2
LCD32B Power Control Register
4 MEMORY AND BUS
4-7
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