I2C Ch.n Mode Register; I2C Ch.n Baud-Rate Register - Epson S1C31W74 Technical Manual

Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the I2C operating clock is supplied during debugging or not.
1 (R/W): Clock supplied during debugging
0 (R/W): No clock supplied during debugging
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits select the division ratio of the I2C operating clock.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of the I2C.
I2C_nCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The I2C_nCLK register settings can be altered only when the I2C_nCTL.MODEN bit = 0.

I2C Ch.n Mode Register

Register name Bit
I2C_nMOD 15–8 –
7–3 –
2
1
0
Bits 15–3 Reserved
Bit 2 OADR10
This bit sets the number of own address bits for slave mode.
1 (R/W): 10-bit address
0 (R/W): 7-bit address
Bit 1 GCEN
This bit sets whether to respond to master general calls in slave mode or not.
1 (R/W): Respond to general calls.
0 (R/W): Do not respond to general calls.
Bit 0 Reserved
Note: The I2C_nMOD register settings can be altered only when the I2C_nCTL.MODEN bit = 0.

I2C Ch.n Baud-Rate Register

Register name Bit
I2C_nBR 15–8 –
7
6–0 BRT[6:0]
Bits 15–7 Reserved
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
Table 16.7.1 Clock Source and Division Ratio Settings
0x0
IOSC
1/8
1/4
1/2
1/1
Bit name Initial
0x00
0x00
OADR10 0
GCEN 0
– 0
Bit name Initial
0x00
– 0
0x7f
Seiko Epson Corporation
I2C_nCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/1 1/8
1/4
1/2
1/1
Reset R/W
– R –
– R
H0 R/W
H0 R/W
– R
Reset R/W
– R –
– R
H0 R/W
16 I 2 C (I2C)
0x3
EXOSC
1/1
Remarks
Remarks
16-19