Epson S1C31W74 Technical Manual page 170

Cmos 32-bit single chip microcontroller
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S1C31 QSPI
(memory mapped
access mode)
Figure 15.2.2.1 Connections between QSPI in Memory Mapped Access Mode
S1C31 QSPI
(register access
master mode)
Figure 15.2.2.2 Connections between QSPI in Register Access Master Mode
S1C31 QSPI
(register access
master mode)
Figure 15.2.2.3 Connections between QSPI in Register Access Master Mode
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
#QSPISSn
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
QSPICLKn
and an External QSPI Slave Device
#QSPISSn
Px1
Px2
QSDIOn1
QSDIOn0
QSPICLKn
and External Single-I/O SPI (Legacy SPI) Slave Devices
#QSPISSn
Px1
Px2
QSDIOn1
QSDIOn0
QSPICLKn
and External Dual-I/O SPI Slave Devices
Seiko Epson Corporation
15 QUAD SYNCHRONOUS SERIAL INTERFACE (QSPI)
#QSPISS
QSDIO3
QSDIO2
QSDIO1
QSDIO0
QSPICLK
#SPISS
SDO
SDI
SPICK
#SPISS
SDO
External single-I/O
SPI slave devices
SDI
SPICK
#SPISS
SDO
SDI
SPICK
#SPISS
SDIO1
SDIO0
SPICK
#SPISS
SDIO1
External dual-I/O
SPI slave devices
SDIO0
SPICK
#SPISS
SDIO1
SDIO0
SPICK
External QSPI
slave device
15-3

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