Svd2 Operations - Epson S1C31W74 Technical Manual

11 SUPPLY VOLTAGE DETECTOR (SVD2)

11.4.2 SVD2 Operations

Continuous operation mode
SVD2 Ch.n operates in continuous operation mode by default (SVD2_nCTL.SVDMD[1:0] bits = 0x0). In this
mode, SVD2 Ch.n operates continuously while the SVD2_nCTL.MODEN bit is set to 1 and it keeps loading
the detection results to the SVD2_nINTF.SVDDT bit. During this period, the current detection results can be
obtained by reading the SVD2_nINTF.SVDDT bit as necessary. Furthermore, an interrupt (if the SVD2_nCTL.
SVDRE[3:0] bits ≠ 0xa) or a reset (if the SVD2_nCTL.SVDRE[3:0] bits = 0xa and the SVD2_nCTL.SVDF
bit = 0) can be generated when the SVD2_nINTF.SVDDT bit is set to 1 (power supply voltage drop or rise is
detected). This mode can keep detecting power supply voltage drop or rise after the voltage detection masking
time has elapsed even if the IC is placed into SLEEP status or accidental clock stoppage has occurred.
Intermittent operation mode
SVD2 Ch.n operates in intermittent operation mode when the SVD2_nCTL.SVDMD[1:0] bits are set to 0x1 to
0x3. In this mode, SVD2 Ch.n turns on at an interval set using the SVD2_nCTL.SVDMD[1:0] bits to perform
detection operation and then it turns off while the SVD2_nCTL.MODEN bit is set to 1. During this period, the
latest detection results can be obtained by reading the SVD2_nINTF.SVDDT bit as necessary. Furthermore, in
power supply drop detection mode, an interrupt or a reset can be generated when SVD2 Ch.n has successively
detected drop of power supply voltage the number of times specified by the SVD2_nCTL.SVDSC[1:0] bits. In
power supply rise detection mode, an interrupt can be generated when SVD2 Ch.n has successively detected
rise of the power supply voltage the number of the specified times.
(1) When the SVD2_nCTL.SVDF bit = 0 (power supply voltage drop detection mode) and the SVD2_nCTL.
SVDMD[1:0] bits = 0x0 (continuous operation mode)
SVD2_nCTL.MODEN
Voltage detection operating status
SVD2_nINTF.SVDDT
Power supply voltage drop
detection interrupt
(2) When the SVD2_nCTL.SVDF bit = 0 (power supply voltage drop detection mode) and the SVD2_nCTL.
SVDMD[1:0] bits ≠ 0x0 (intermittent operation mode)
SVD2_nCTL.MODEN
Voltage detection operating status
SVD2_nINTF.SVDDT
Power supply voltage drop
detection interrupt
(3) When the SVD2_nCTL.SVDF bit = 1 (power supply voltage rise detection mode) and the SVD2_nCTL.
SVDMD[1:0] bits = 0x0 (continuous operation mode)
SVD2_nCTL.MODEN
Voltage detection operating status
SVD2_nINTF.SVDDT
Power supply voltage rise
detection interrupt
(4) When the SVD2_nCTL.SVDF bit = 1 (power supply voltage rise detection mode) and the SVD2_nCTL.
SVDMD[1:0] bits ≠ 0x0 (intermittent operation mode)
SVD2_nCTL.MODEN
Voltage detection operating status
SVD2_nINTF.SVDDT
Power supply voltage rise
detection interrupt
11-4
V
DD
V
DD
DET
V
DD
V
DD
DET
V : Level set using the SVD2_nCTL.SVDC[4:0] bits
SVD
: Voltage detection masking time
DET
: Voltage detection operation
Figure 11.4.2.1 SVD2 Operations
Seiko Epson Corporation
V V
SVD SVD
DET
V V
SVD SVD
DET
V V
SVD SVD
DET
V V
SVD SVD
DET
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)