Epson S1C31W74 Technical Manual page 160

Data reception
(
Assert the slave select signal output from
a general-purpose port
Read the SPIA_nINTF.TBEIF bit
SPIA_nINTF.TBEIF = 1 ?
YES
Write dummy data (or transmit data) to
the SPIA_nTXD register
Wait for an interrupt request
(SPIA_nINTF.RBFIF = 1)
Read receive data from
the SPIA_nRXD register
Receive data remained?
NO
(
Negate the slave select signal output from
a general-purpose port
End
(A) Intermittent data reception
Data reception using DMA
For data reception, two DMA controller channels should be used to write dummy data to the SPIA_nTXD reg-
ister as a reception start trigger and to read the received data from the SPIA_nRXD register.
By setting the SPIA_nTBEDMAEN.TBEDMAENx
request is sent to the DMA controller and dummy data is transferred from the specified memory to the SPIA_
nTXD register via DMA Ch.x
By setting the SPIA_nRBFDMAEN.RBFDMAENx
request is sent to the DMA controller and the received data is transferred from the SPIA_nRXD register to the
specified memory via DMA Ch.x
This automates the procedure from Step 2 to Step 8 described above.
The transfer source/destination and control data must be set for the DMA controller and the relevant DMA
channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the "DMA
Controller" chapter.
Table 14.5.3.1 DMA Data Structure Configuration Example (for Writing 16-bit Dummy Transmit Data)
Item
End pointer Transfer source
Transfer destination SPIA_nTXD register address
Control data dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
) (
Assert the slave select signal output from
Read the SPIA_nINTF.TBEIF bit
NO
Write dummy data (or transmit data) to
Write dummy data (or transmit data) to
YES
)
(
Negate the slave select signal output from
(B) Continuous data reception
Figure 14.5.3.2 Data Reception Flowcharts in Master Mode
when the SPIA_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
1
when the SPIA_nINTF.RBFIF bit is set to 1 (receive buffer full).
2
Memory address in which dummy data is stored
0x3 (no increment)
0x1 (haflword)
0x3 (no increment)
0x1 (halfword)
0x0 (arbitrated for every transfer)
Number of transfer data
0x1 (basic transfer)
Seiko Epson Corporation
14 SYNCHRONOUS SERIAL INTERFACE (SPIA)
Data reception
a general-purpose port
SPIA_nINTF.TBEIF = 1 ?
YES
the SPIA_nTXD register
Wait for an interrupt request
(SPIA_nINTF.TBEIF = 1)
the SPIA_nTXD register
Wait for an interrupt request
(SPIA_nINTF.RBFIF = 1)
Read receive data from
the SPIA_nRXD register
Receive data remained?
NO
a general-purpose port
End
bit to 1 (DMA transfer request enabled), a DMA transfer
1
bit to 1 (DMA transfer request enabled), a DMA transfer
2
Setting example
)
NO
Execute this sequence
within theSPICLKn
cycles equivalent to
"Data bit length - 1" from
an interrupt request
YES
)
14-9