Figure 2-2 Typical Swd Connections; Swd Timing Requirements; Table - ARM DS-5 Manual

2.1.2 Serial Wire Debug
This describes the Serial Wire Debug (SWD) connection to the Debug Access Port (DAP).
SWD connections
The diagram shows a typical Serial Wire Debug (SWD) connection scheme.
• The SWDIO, SWCLK and SWO signals are typically pulled up on the target to keep them stable
when the debug equipment is not connected.
• All pull-up resistors must be in the range 1K-100KΩ.
• The VTREF signal is typically connected directly to the VDD rail. If you use a series resistor to
protect against short-circuits, it must have a value no greater than 100Ω.
• To improve signal integrity, it is good practice to provide an impedance matching resistor on the
SWDIO and SWO outputs of the processor. The value of these resistors, added to the impedance of
the driver must be approximately equal to 50Ω.
Related concepts
2.1.1 JTAG port timing characteristics on page 2-23.
SWD timing requirements on page 2-25.
2.1.3 About trace signals on page 2-26.
Related references
2.1.2 Serial Wire Debug on page 2-25.

SWD timing requirements

The SWD interface uses only two lines, SWDIO and SWDCLK.
For clarity, the diagrams shown in the following figure separate the SWDIO line to show when it is
driven by either the DSTREAM probe or target:
ARM 100956_0527_00_en
VTREF
SWDIO
SWCLK
SWO
nSRST
GND
Note
Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved.
2 ARM DSTREAM Target Interface Connections
VDD
Gnd
Non-Confidential
2.1 Signal descriptions
Processor/
22R
SWDIO
SWCLK
22R
SWO
Reset
RESET
circuit

Figure 2-2 Typical SWD connections

ARM
ASIC
2-25