Ieee1394Link/Transaction Controller Xcsbuf Area (Sram) - Epson S1R75801F00A Technical Manual

7.1.2 IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM)

0x400000
0x4000C0
0x4000E0
0x400100
0x401FFF
TxHeaderArea
TxAreaStart
+ 0x20
+ 0x40
• All RAM areas are accessible from the CPU by direct
addressing.
• Hardware DMA is possible to the IDE I/F for the
RxStreamArea and TXStreamArea.
• HW_PageTableArea (the equivalent of 24 pages)
and HW_RxHeaderArea and HW_TXHeaderArea
(the equivalent of 1 header, respectively) are assured.
The RxORB and TxORB areas are usable by firmware
alone.
• The RxHeaderArea, RxORBArea, TxORB,
TXStreamArea and RxStreamArea are RingBuffers.
Even at the time of execution of data transmission/
reception according to 1394 or IDE DMA, data
among the areas are guaranteed by hardware . (The
size of each RingBuffer is variable by settings on the
8KBytes
HW_PageTableArea
HW_RxHeaderArea
HW_TxHeaderArea
RxHeaderArea
(RingBuffer)
RxORBArea
(RingBuffer)
TxHeaderArea (2 Headers)
TxORBArea
(RingBuffer)
TxStreamArea
(RingBuffer)
NotUsed
RxStreamArea
(RingBuffer)
used Asyncronouse only
AsyTxPktHdr 0
AsyTxPktHdr 1
EPSON
(RxHeaderAreaStart)
RxORBAreaStart
TxHeaderAreaStart
(TxHeaderAreaStart + 0x0040)
TxStreamAreaStart
IDE – > 1394 DMA Area
TxStreamAreaEnd
RxStreamAreaStart
1394 – > IDE DMA Area
used Isocronouse
TxAreaStart
AsyTxPktHdr 0
+ 0x20
IsoTxPktHdr 0
+ 0x30
IsoTxPktHdr 1
+ 0x40
TxStreamAreaStart, TxStreamAreaEnd, and
RxStreamAreaStart.)
• The TxStreamArea and RxStreamArea is usable as
one StreamArea by overlaying them.
• The Post**Ptr and Used**Ptr of the RxHeaderArea,
RxORBArea, TxStreamArea, and RxStreamArea
monitor the used condition in each Area.
(In the case of the Rx of 1394, the free space of the
above two is monitored and the busy_A, B, X is
controlled by hardware.)
• By controlling the above functions from the TRAN &
SBP2 Control Block, a PageTable fetch and data
transfer according to SBP-2 are executable by
hardware.
S1R72803F00A
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