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3. Intel Agilex Configuration Schemes
3.1. Avalon-ST Configuration
The Avalon-ST configuration scheme replaces the FPP mode available in earlier device families. Avalon-ST is the fastest
configuration scheme for Intel Agilex devices. This scheme uses an external host, such as a microprocessor, MAX
or Intel MAX 10 device to drive configuration. The external host controls the transfer of configuration data from external
storage such as flash memory to the FPGA. The logic that controls the configuration process resides in the external host. You
can use the PFL II IP with a MAX II, MAX V, or Intel MAX 10 device as the host to read configuration data from the flash
memory device and configure the Intel Agilex device. The Avalon-ST configuration scheme is called passive because the
external host, not the Intel Agilex device, controls configuration.
Table 14.
Avalon-ST Configuration Data Width, Clock Rates, and Data Rates
Mbps is an abbreviation for Megabits per second.
Protocol
Avalon-ST
Table 15.
Required Configuration Signals for the Avalon-ST Configuration Scheme
You can use an 8-, 16-, or 32-bit Avalon-ST configuration data bus. You specify SDM I/O pin functions using the Device
Configuration dialog box in the Intel Quartus Prime software. For the Avalon-ST x16 and x32 configuration, you can reassign the GPIO, dual-purpose
configuration pins for other functions in user mode using the Device
Signal Name
nSTATUS
nCONFIG
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Data Width (bits)
Max Clock Rate
32
16
8
Pin Type
SDM I/O
SDM I/O
Max Data Rate
125 MHz
4000 Mbps
125 MHz
2000 Mbps
125 MHz
1000 Mbps
Device and Pin Options
Dual-Purpose Pins dialog box.
Direction
Output
Input
®
II, MAX V,
MSEL[2:0]
000
101
110
Device and Pin Options
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CCIO_SDM
V
CCIO_SDM
continued...
ISO
9001:2015
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