Intel Agilex Series Configuration User Manual page 86

Figure 31. Cypress and Micron M28, M29 Flash Memory in 16-Bit Mode
The address bit numbers in the PFL II IP core and the flash memory device are the same.
3.1.7.3.3. Creating a Single PFL II IP for Programming and Configuration
Follow these steps to create a single PFL II IP instantiation for programming and configuration control:
1. In the IP Catalog locate the Parallel Flash Loader II Intel FPGA IP.
2. On the General tab for What operating mode will be used, select Flash Programming and FPGA Configuration.
3. In the same tab, for What is the targeted flash?, select CFI Parallel Flash.
4. Specify the parameters on the Flash Interface Settings tab:
a. Select 1 for a single flash device.
b. Select CFI 1 Gbit as the largest used flash device.
c. Select 16 bits for the flash interface data width.
5. Specify the parameters on the FPGA Configuration to match your design.
6. Compile and generate a
3.1.7.3.4. Creating Separate PFL II Functions
Follow these steps to create separate PFL II IP instantiations for programming and configuration control:
Intel ® Agilex ™ Configuration User Guide
86
address: 23 bits
PFL II
22
21
20
-
-
-
2
1
0
for the flash memory device. Ensure that you tri-state all unused I/O pins.
.pof
3. Intel Agilex Configuration Schemes
address: 23 bits
Flash Memory
22
21
20
-
-
-
2
1
0
683673 | 2021.10.29
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