Intel Agilex Series Configuration User Manual page 104

For PCIe designs including the Configuration via Protocol (CvP), Intel recommends that you use Micron QSPI flash memory.
When using the Micron QSPI flash memory, the boot ROM uses the AS x4 mode to load the initial configuration firmware
faster to meet the PCIe wake-up time for host enumeration.
When using other flash memory types for PCIe designs, the boot ROM reads the firmware using AS x1 mode. Intel
recommends asserting the
(POR) state. This ensures the PCIe endpoint enters the link training state prior to the
The following block diagram illustrates the components and design flow using the AS configuration scheme.
Figure 37. Components and Design Flow for .jic Programming
In addition to AS programming using a
a as shown in AS Programming Using Intel Quartus Prime or Third-Party Programmer.
.pof
Intel ® Agilex ™ Configuration User Guide
104
signal low for a minimum of 200 ms counting from the device exiting the power-on reset
PERST#
Quartus Software flow on PC
Quartus Prime
Compilation
Quartus Prime:
File Start Compile
SOF
Quartus Prime
Programming File
Generator
Quartus Prime:
File Programming File Generator
, the Programmer supports direct programming of the quad SPI flash using
.jic
PERST#
Intel FPGA
QSPI
SDM
10 pin JTAG header
Intel FPGA Download Cable II
USB
Quartus Prime
JIC
Programmer
Quartus Prime:
Tools Programming
3. Intel Agilex Configuration Schemes
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signal deasserts.
Board
Flash
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