Intel Agilex Series Configuration User Manual page 230

Document Version Intel Quartus
Prime Version
2019.04.03
2019.04.02
Intel ® Agilex ™ Configuration User Guide
230
•
Removed vector for
Power_Supply_Status
•
Corrected the Intel Agilex FPGA Configuration Flow diagram. The transition between
should say
INIT_DONE = HIGH
•
Corrected the following statement in the Debugging Guidelines for the JTAG Configuration Scheme topic: An
falling edge terminates any JTAG access and the device reverts to the
stable during JTAG configuration.. In both sentence,
•
Removed pin assignments for
Configuration Signals that Do Not Use Dedicated SDM I/O Pins table. CvP does not the support Avalon-ST x8 configuration
scheme in Intel Agilex devices.
19.1 Removed references to documents that are not yet available.
19.1 Initial Release
9. Document Revision History for the Intel Agilex Configuration User Guide
Changes
in the Configuration, Reconfiguration, and Error Timing Diagram figure.
.
should be
nSTATUS
for the Avalon-ST in the Available SDM I/O Pin Assignments for
CVP_CONFDONE
683673 | 2021.10.29
and
FPGA Config* User Mode
-specified boot source.
MSEL nSTATUS
.
nCONFIG
Send Feedback
nSTATUS
must be