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Intel Agilex Series Configuration User Manual

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Agilex
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Configuration User Guide
Prime Design Suite: 21.3
UG-20205
ID:
683673
Version:
2021.10.29

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Summary of Contents for Intel Agilex Series

  • Page 1 ® ™ Intel Agilex Configuration User Guide ® ® Updated for Intel Quartus Prime Design Suite: 21.3 683673 Online Version Send Feedback Version: 2021.10.29 UG-20205...

  • Page 2: Table Of Contents

    3.1.4. RBF Configuration File Format...........................60 3.1.5. Avalon-ST Single-Device Configuration.......................61 3.1.6. Debugging Guidelines for the Avalon-ST Configuration Scheme................64 3.1.7. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core....... 65 3.2. AS Configuration............................... 102 Intel ®...
  • Page 3 3.3.3. JTAG Multi-Device Configuration........................130 3.3.4. Debugging Guidelines for the JTAG Configuration Scheme...................132 4. Including the Reset Release Intel FPGA IP in Your Design....................134 4.1. Understanding the Reset Release IP Requirement......................135 4.2. Instantiating the Reset Release IP In Your Design......................137 4.3.
  • Page 4 6.2. Configuration via Protocol............................207 6.3. Partial Reconfiguration............................... 209 7. Intel Agilex Debugging Guide............................. 210 7.1. Configuration Debugging Checklist..........................210 7.2. Intel Agilex Configuration Architecture Overview......................212 7.3. Understanding Configuration Status Using quartus_pgm command.................. 212 7.4. Configuration File Format Differences...........................213 7.5. Understanding SEUs..............................214 7.6.
  • Page 5 Contents 8. Intel Agilex Configuration User Guide Archives........................217 9. Document Revision History for the Intel Agilex Configuration User Guide................218 Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 6: Intel ® Agilex ™ Configuration User Guide

    FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or 9001:2015 service described herein except as expressly agreed to in writing by Intel.
  • Page 7 You can configure the Intel Agilex device using the dedicated JTAG pins. The JTAG port provides seamless access to many useful tools and functions. In addition to configuring the Intel Agilex, you use the JTAG port for debugging with Signal Tap or the System Console tools.
  • Page 8 MSEL CvP uses an external PCIe* host device as a Root Port to configure the Intel Agilex device over the PCIe link. You can specify up to a x16 PCIe link. Intel Agilex devices support two CvP modes, CvP initialization and CvP update.

  • Page 9: Configuration And Related Signals

    Intel Agilex device accesses flash memory immediately after exiting reset. The power supply must be able to provide an equally fast ramp up for the Intel Agilex device and the external AS x4 flash devices. Failing to meet this requirement causes the SDM to report that the memory is missing.

  • Page 10: Intel Download Cables Supporting Configuration In Intel Agilex Devices

    VCCBAT PWRMGT_ALERT This user guide discusses most of the interfaces shown in the figure. Refer to the separate Intel Agilex Configuration via Protocol (CvP) Implementation User Guide and Intel Agilex Power Management User Guide for more information about those features.
  • Page 11 Table 2. Intel Agilex-Supported Download Cable Capabilities Download Cable Protocol Support Intel Agilex Device Cable Connection to PCB Intel FPGA Download Cable II (formerly the USB-Blaster JTAG, AS 10-pin female plug Intel FPGA Ethernet Cable (formerly the Ethernet JTAG, AS...

  • Page 12: Intel Agilex Configuration Architecture

    The Secure Device Manager (SDM) is a triple-redundant processor-based module that manages configuration and the security features of Intel Agilex devices. The SDM is available on all Intel Agilex FPGAs and SoC devices. The block diagram below provides an overview of the Intel Agilex configuration architecture which includes the following blocks: •...
  • Page 13 Sector Local Sector Local Sector Manager (LSM) Manager (LSM) Configuration Configuration Sector Sector Related Information Intel Agilex FPGAs and SoC Device Overview Provides information about available Intel Agilex transceiver tile variants. Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 14: Secure Device Manager

    SDM Block Diagram figure. The SDM performs and manages the following security functions: • Configuration bitstream authentication: During the configuration state, the SDM authenticates the Intel-generated configuration firmware and configuration bitstream, ensuring that configuration bitstream is from a trusted source. All Intel Agilex support authentication.
  • Page 15 ® ™ 1. Intel Agilex Configuration User Guide 683673 | 2021.10.29 Figure 3. SDM Block Diagram FPGA Core Secure Device Manager OCRAM Communication Lockstep Processors Sensors Boot ROM Temperature SEU Detection Voltage Chip ID Serial Flash Peripherals Crypto IP Mailbox Client IP...
  • Page 16 When you generate a configuration bitstream using the File Programming File Generator menu item, the bitstream assembler adds all firmware (including the SDM firmware) that matches the Intel Quartus Prime Pro Edition Release to the bitstream generated from the .sof Depending on the configuration scheme you specify the resulting file can be in any of the following formats: •...
  • Page 17 For information about the programming file generator output file types. 1.2.1.2. Specifying Boot Order for Intel Agilex SoC Devices For Intel Agilex SoC devices you can specify the configuration order, choosing either the FPGA First or the Hard Processor System (HPS) First options.

  • Page 18: Intel Agilex Configuration Details

    FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or 9001:2015 service described herein except as expressly agreed to in writing by Intel.
  • Page 19 The SDM drives Intel Agilex device configuration. Power-On Status The power-on reset (POR) holds the Intel Agilex device in the reset state until the power supply outputs are within the recommended operating range. defines the maximum power supply ramp time. If power supplies ramp time do not...
  • Page 20 Reset Release nINIT_DONE Intel FPGA IP to hold your application logic in the reset state until the entire FPGA fabric is in user mode. Failure to include this IP in your design may result in intermittent application logic failures.
  • Page 21 The numbers in the Configuration Error part of the timing diagram mark the following events: 1. The SDM drives signal low for a period of time specified in the Intel Agilex Device Datasheet to indicate a nSTATUS recoverable configuration error. The Intel Agilex device may not assert...
  • Page 22 In rare instances, a configuration error or a security event may be unrecoverable. In these cases, the SDM drives nSTATUS low and it stays low. You must perform a power cycle to restart the reconfiguration process. To ensure error recovery under all reconfiguration circumstances, Intel recommends that you design your system to continuously monitor and enable nSTATUS device power cycling if needed.

  • Page 23: Configuration Flow Diagram

    Intel Device Datasheet. Note: You can perform JTAG configuration anytime from any state if the device is powered up and the power is intact. The Intel Agilex device cancels the previous configuration and accepts the reconfiguration data from the JTAG interface. The nCONFIG signal must be held in a stable state during JTAG configuration.
  • Page 24 683673 | 2021.10.29 Power-On • The Intel Agilex power supplies follow the guidelines in the Power-Up Sequence Requirements for Intel Agilex Devices section of the Intel Agilex Power Management User Guide. • A device-wide power-on reset (POR) asserts after the power supplies reach the correct operating voltages. The external power supply ramp must not be slower than the minimum ramping rate until the supplies reach the operating voltage.
  • Page 25 2. Intel Agilex Configuration Details 683673 | 2021.10.29 • The power management activity is ongoing during the device configuration. For more information, refer to the Intel Agilex Power Management User Guide. • The SDM drives the pin high after successfully receiving full bitstream.

  • Page 26: Device Response To Configuration And Reset Events

    Intel Agilex Power Management User Guide 2.4. Additional Clock Requirements for HPS and Transceivers The Intel Agilex device has specific clock requirements for transceivers and HPS EMIF IP. These clock requirements must be met before the FPGA configuration begins. Intel ®...
  • Page 27 HPS First Configuration Intel Agilex devices have the option of booting the HPS before configuring the FPGA core logic. This method is known as the HPS first configuration. When you choose this option in the Intel Quartus Prime Pro Edition software, the following clocks must be operational prior to the FPGA I/O, HPS I/O, and HPS boot, also called a phase 1 configuration: •...

  • Page 28: Intel Agilex Configuration Pins

    2 configuration. 2.5. Intel Agilex Configuration Pins The Intel Agilex device uses SDM_IO pins for device configuration. Control of SDM I/O pins passes from internal FPGA circuitry, to the Boot ROM, and finally to the value your application logic specifies.

  • Page 29: Msel Settings

    — SDM_IO16 2.5.2. MSEL Settings After power-on pins specify the configuration scheme for Intel Agilex devices. Use 4.7-kΩ resistors to pull the MSEL[2:0] pins up to V or down to ground as required by the setting for your configuration scheme.
  • Page 30 If you use AS Fast mode, you must ramp all power supplies to the recommended operating condition within 10 ms. This ramp-up requirement ensures that the AS x4 device is within its operating voltage range when the Intel Agilex device begins to access it.

  • Page 31: Device Configuration Pins For Optional Configuration Signals

    2.5.3. Device Configuration Pins for Optional Configuration Signals All configuration schemes use the same dedicated pins for the standard control signals shown in the Intel Agilex Configuration Timing Diagram. Many other optional configuration signals do not have dedicated pin assignments.
  • Page 32 2. Intel Agilex Configuration Details 683673 | 2021.10.29 Configuration Scheme Signal Names Avalon-ST AS x4 CONF_DONE SDM_IO0 SDM_IO0 SDM_IO0 SDM_IO0 SDM_IO5 SDM_IO1 SDM_IO1 SDM_IO10 SDM_IO12 SDM_IO2 SDM_IO2 SDM_IO11 SDM_IO16 SDM_IO3 SDM_IO3 SDM_IO12 SDM_IO4 SDM_IO4 SDM_IO13 SDM_IO5 SDM_IO5 SDM_IO14 SDM_IO6 SDM_IO6...
  • Page 33 2. Intel Agilex Configuration Details 683673 | 2021.10.29 Configuration Scheme Signal Names Avalon-ST AS x4 SDM_IO16 SDM_IO16 Not supported Not supported Not supported CVP_CONFDONE SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO16 SEU_ERROR SDM_IO0 SDM_IO0 SDM_IO0 SDM_IO0 SDM_IO5 SDM_IO1 SDM_IO1 SDM_IO10...
  • Page 34 2. Intel Agilex Configuration Details 683673 | 2021.10.29 Configuration Scheme Signal Names Avalon-ST AS x4 SDM_IO6 SDM_IO6 SDM_IO16 SDM_IO7 SDM_IO7 SDM_IO9 SDM_IO9 SDM_IO10 SDM_IO10 SDM_IO11 SDM_IO11 SDM_IO12 SDM_IO12 SDM_IO13 SDM_IO13 SDM_IO14 SDM_IO14 SDM_IO15 SDM_IO15 SDM_IO16 SDM_IO16 Not applicable Not applicable...
  • Page 35 SDM I/O pins 0 or 16. These pins have weak CONF_DONE INIT_DONE internal pull-downs resistors. If you cannot use these pins, Intel recommends that you include external 4.7-kΩ pull-down resistors to avoid false signaling. Related Information Intel Agilex Power Management User Guide...
  • Page 36 2. Intel Agilex Configuration Details 683673 | 2021.10.29 4. Click OK to confirm and close the Configuration Pin dialog box. 2.5.3.1.1. nCONFIG pin is a dedicated, input pin of the SDM. has two functions: nCONFIG nCONFIG • Hold-off initial configuration •...
  • Page 37 AVST_READY asserts if an error occurs during configuration. The pulse ranges from 0.5 ms to 10 ms. nSTATUS assertion is asynchronous to data error detection. Intel Agilex devices do not support the auto-restart nSTATUS configuration after error option. Previous device families implement the as an open drain with a weak internal pull-up.
  • Page 38 , weak internal pull-downs pull these pins low CONF_DONE INIT_DONE SDM_IO16 SDM_IO0 at power-on reset. Ensure you specify these pins in the Intel Quartus Prime Software or in the Intel Quartus Prime settings file, ( are low prior to and during configuration. asserts when the device .qsf...
  • Page 39 2. Intel Agilex Configuration Details 683673 | 2021.10.29 Figure 10. Configuration Pin Selection in the Intel Quartus Prime Pro Edition Software Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 40 2. Intel Agilex Configuration Details 683673 | 2021.10.29 Figure 11. Fitter Report and SDM_IO Pin Reporting 2.5.3.2. Enabling Dual-Purpose Pins , and are dual-purpose pins. Once the device enters user AVST_CLK AVST_DATA[15:0] AVST_DATA[31:16] AVST_VALID mode these pins can function either as GPIOs or as tri-state inputs.
  • Page 41 2.5.3.3. I/O Standards and Features for Intel Agilex Configuration Pins The SDM pins have different I/O standards and features in different Intel Agilex configuration schemes. You can assign the unused SDM pins for other functions in the Intel Quartus Prime software.
  • Page 42 2. Intel Agilex Configuration Details 683673 | 2021.10.29 Table 7. Intel Agilex AS ×4 Configuration Scheme—Dedicated Configuration Pins Pin Function SDM I/O Direction I/O Standard Schmitt Trigger/TTL Weak Drive Open Drain Slew Input Pull-Up/ Strength Rate Pull-Down Bidirectional 1.8 V LVCMOS...
  • Page 43 2. Intel Agilex Configuration Details 683673 | 2021.10.29 Table 9. Intel Agilex Avalon Streaming Interface ×8 Configuration Scheme—Dedicated Configuration Pins Pin Function SDM I/O Direction I/O Standard Schmitt Weak Pull-Up/ Drive Open Drain Slew Trigger/TTL Pull-Down Strength Rate Input Input 1.8 V LVCMOS...
  • Page 44 1.2 V LVCMOS — — AVST_DATA Table 12. Intel Agilex Optional Configuration Pins The SDM I/O for each pin function in this table is as assigned in the Intel Quartus Prime configuration pins option. Pin Function Direction I/O Standard Schmitt Weak Pull-Up/...
  • Page 45 Fast TAMPERRESPONSESTATUS 2.5.3.3.1. IBIS Model You can download the IBIS models from the IBIS Models for Intel Devices web page. The Intel Quartus Prime software does not support IBIS model generation for configuration pins in the current release. Related Information IBIS Models for Intel Devices 2.5.3.4.
  • Page 46 683673 | 2021.10.29 Intel Quartus Prime Pro Edition software allows you to control the payload value of the Page command. Some PMBus devices contain more than one page per bank of registers, the Page command allows you to select the target Page per bank registers.
  • Page 47 2. Intel Agilex Configuration Details 683673 | 2021.10.29 Related Information Intel Agilex Power Management User Guide Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 48: Configuration Clocks

    PR_READY • PR_ERROR • PR_DONE Connect these partial reconfiguration signals to the Partial Reconfiguration External Configuration Controller Intel FPGA IP. Related Information Creating a Partial Reconfiguration Design 2.6. Configuration Clocks 2.6.1. Setting Configuration Clock Source You must specify the configuration clock source by selecting either the internal oscillator or...

  • Page 49: Osc_Clk_1 Clock Input

    Intel Quartus Prime OSC_CLK_1 OSC_CLK_1 software, the device loads the majority of the configuration bitstream at 250 MHz. Intel Agilex devices include an internal oscillator in addition to which runs the configuration process at a frequency between 160-230 MHz. Intel Agilex OSC_CLK_1 devices always use this internal oscillator to load the first section of the bitstream, up to a maximum of 512 kilobyte (KB).

  • Page 50: Intel Agilex Configuration Time Estimation

    This section describes configuration time for various configuration modes for different bitstream sizes. For example, in PCIe designs, your system software may require the Intel Agilex device to enter user mode in less than 1 second to return a successful completion status for a valid configuration request. Use the values referenced below to determine the configuration mode that best suits your design requirements.

  • Page 51: Generating Compressed .Sof File

    AGF 012 AGF 014 AGI 022 AGI 027 1,200 2.8. Generating Compressed File .sof Intel Quartus Prime Pro Edition software allows you to generate a compressed file. The compressed file size is .sof .sof smaller compared to the non-compressed file. .sof...
  • Page 52 2. Intel Agilex Configuration Details 683673 | 2021.10.29 Figure 14. Compressed Selection in the Intel Quartus Prime Pro Edition .sof Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 53: Intel Agilex Configuration Schemes

    FPGA. The logic that controls the configuration process resides in the external host. You can use the PFL II IP with a MAX II, MAX V, or Intel MAX 10 device as the host to read configuration data from the flash memory device and configure the Intel Agilex device.
  • Page 54 If you create custom logic instead of using the PFL II IP to drive configuration, refer to the Avalon Streaming Interfaces in the Avalon Interface Specifications for protocol details. is required if you are using the Intel FPGA Parallel Flash Loader II IP as the configuration host. CONF_DONE Intel ®...

  • Page 55: Avalon-St Configuration Scheme Hardware Components And File Types

    A custom host, typically a microprocessor, with any external memory • The Intel FPGA Download Cable II to connect the Intel Quartus Prime Programmer to the PCB. The following block diagram illustrates the components and design flow using the Avalon-ST configuration scheme.
  • Page 56 Output File Types Programming File Type Extension Description Programmer Object File is a proprietary Intel FPGA file type. Use the PFL II IP core via a JTAG header to write .pof .pof to an external CFI flash or serial flash device. .pof...

  • Page 57: Enabling Avalon-St Device Configuration

    Note: Intel Agilex devices using Avalon ST x32 configuration and DDR x72 external memory interfaces are limited to a maximum of three memory interfaces. The Avalon ST x8 and x16 can support up to four DDR x72 external memory interfaces.
  • Page 58 The configuration files for Intel Agilex devices can be highly compressed. During configuration, the decompression of the bit stream inside the device requires the host to pause before sending more data. The Intel Agilex device asserts the signal when the device is ready to accept data. The...
  • Page 59 If you use the PFL II IP core as the configuration host, you can use the Intel Quartus Prime software to store the binary configuration data to the flash memory through the PFL II IP core.

  • Page 60: Rbf Configuration File Format

    Avalon-ST Configuration Timing For Avalon-ST Timing Parameters for Configuration in Intel Agilex Devices. 3.1.4. RBF Configuration File Format If you do not use the Parallel Flash Loader II Intel FPGA IP core to program the flash, you must generate the file. .rbf...

  • Page 61: Avalon-St Single-Device Configuration

    3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 3.1.5. Avalon-ST Single-Device Configuration Figure 17. Connections for Avalon-ST x8 Single-Device Configuration CCIO_SDM Configuration CCIO_SDM Control Signals 10kΩ External Host 10kΩ Intel FPGA CPLD / FPGA fpga_nconfig nCONFIG fpga_nstatus nSTATUS fpga_conf_done CONF_DONE...
  • Page 62 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 18. Connections for Avalon-ST x16 Single-Device Configuration CCIO_SDM CCIO_SDM 10kΩ External Host Configuration 10kΩ Control Signals Intel FPGA CPLD / FPGA fpga_nconfig nCONFIG nSTATUS fpga_nstatus CONF_DONE fpga_conf_done INIT_DONE Parallel Flash Loader II IP...
  • Page 63 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 19. Connections for Avalon-ST x32 Single-Device Configuration CCIO_SDM CCIO_SDM Configuration External Host 10kΩ Control Signals 10kΩ Intel FPGA CPLD / FPGA fpga_nconfig nCONFIG fpga_nstatus nSTATUS CONF_DONE fpga_conf_done INIT_DONE Parallel Flash Loader II IP...

  • Page 64: Debugging Guidelines For The Avalon-St Configuration Scheme

    If using x16 or x32 mode, power the I/O bank containing the x16 or x32 pins (I/O Bank 3A) at 1.2 V. • Ensure you select the appropriate Avalon-ST configuration scheme in your Intel Quartus Prime Pro Edition project. •...

  • Page 65: Ip For Use With The Avalon-St Configuration Scheme: Intel Fpga Parallel Flash Loader Ii Ip Core

    3.1.7. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core 3.1.7.1. Functional Description You can use the Parallel Flash Loader II Intel FPGA IP (PFL II) with an external host, such as the MAX II, MAX V, or Intel MAX 10 devices to complete the following tasks: •...
  • Page 66 MT28EW CFI flash memory devices to the host in parallel using the same data bus, clock, and control signals. Intel does not support connecting two of non-MT28W CFI flash memory devices to PFL II IP core in parallel. During FPGA...
  • Page 67 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 21. PFL II IP core with Dual MT28EW CFI Flash Memory Devices The flash memory devices must have the same memory density from the same device family and manufacturer. CFI Compliant Flash...
  • Page 68 0×2000 • Auto mode—allows the Intel Quartus Prime software to automatically determine the start address of the page. The Intel Quartus Prime software aligns the pages on a 128 KB boundary. If the first valid start address is , the next valid...
  • Page 69 683673 | 2021.10.29 You set the option bits in the PFL II IP Intel FPGA IP using the parameter editor. By default the PFL II IP displays Flash Programming for the What operating mode will be used? parameter. In this default state, the FPGA Configuration tab is not visible.
  • Page 70 EDIT to specify the Start address for the option bits. This Start address must match the address you specify for What is the byte address of the option bits, in hex? when specifying the PFL II IP parameters. The Intel Quartus Prime Programming File Generator generates the information for the version when you convert .pof...
  • Page 71 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Table 19. Option Bits Sector Format Sector Offset Value – Page 0 start address 0x00 0x03 Page 0 end address – 0x04 0x07 Page 1 start address – 0x08 0x0B Page 1 end address –...
  • Page 72 32-bit value of the sector offset address. If you encounter a configuration error you can verify that the generated bitstream addresses match the addresses you specified in the Intel Quartus Prime Software. The following table shows the bit fields of the start address.
  • Page 73 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Sector Offset Value – 0x0C 0x0F 0x00352E30 For Page 0 if you append the start address bits[31:11] with , the result is 13'b0000000000000 32'b00000000000000010000000000000000 = 0x10000 If you append the end address...
  • Page 74 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 24. Implementing Page Mode and Option Bits in the CFI Flash Memory Device 8 Bits End Address Option Bits Configuration Data (Page 2) 32 Bits Configuration Data (Page 1) Page 2 Address + Page-Valid...
  • Page 75 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 25. Page Start Address, End Address, and Page-Valid Bit Stored as Option Bits The Page-Valid bits indicate whether each page is successfully programmed. The PFL II IP core sets the Page-Valid bits after successfully programming the pages.
  • Page 76 This section describes the procedures on how to use the PFL II IP core. To target a MAX II, MAX V, or Intel MAX 10 device requires the use of Intel Quartus Prime Standard Edition whereas targeting a Intel Agilex requires Intel Quartus Prime Pro Edition.
  • Page 77 Create the optional Jam programming file Program the MAX II and Flash Devices MAX II configures the FPGA with the configuration data from the Flash Device Related Information Intel Agilex F-Series Transceiver-SoC Development Kit Intel ® Agilex ™ Configuration User Guide...
  • Page 78 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 3.1.7.2.1. PFL II Parameters Table 23. PFL II General Parameters Options Value Description What operating mode • Flash Programming Specifies the operating mode of flash programming and FPGA configuration control in one will be used? IP core or separate these functions into individual blocks and functionality.
  • Page 79 Specifies the flash access time. This information is available from the flash datasheet. access time? Intel recommends specifying a flash access time that is equal to or greater than the required time. For CFI parallel flash, the unit is in ns. For NAND flash, the unit is in μs. NAND flash uses pages instead of bytes and requires greater access time.
  • Page 80 Intel Burst mode • Normal mode—applicable for all flash memory • 16 byte page mode (GL only) • Intel Burst mode—Applicable for devices that support bursting. Reduces sequential • 32 byte page mode (MT28EW) read access time • Micron Burst Mode (M58BW) •...
  • Page 81 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 3.1.7.2.2. PFL II Signals Table 27. PFL II Signals Type Weak Pull-Up Function Input — Asynchronous reset for the PFL II IP core. Pull high to enable FPGA pfl_nreset configuration. To prevent FPGA configuration, pull low when you do not use the PFL II IP core.
  • Page 82 Do not connect these pins from the flash memory device to the host if you are not using burst mode. continued... (11) Intel recommends that you do not insert logic between the PFL II pins and the host I/O pins, especially on the flash_data pins. fpga_nconfig Intel ®...
  • Page 83 3.1.7.3.1. Controlling Avalon-ST Configuration with PFL II IP Core The PFL II IP core in the host determines when to start the configuration process, read the data from the flash memory device, and configure the Intel Agilex device using the Avalon-ST configuration scheme. Figure 27.
  • Page 84 You have JTAG or In-System Programming (ISP) access to the configuration host. • You want to program the flash memory device with non-Intel FPGA data, for example initialization storage for an ASSP. You can use the PFL II IP core to program the flash memory device for the following purposes: —...
  • Page 85 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 29. Flash Memories in 16-Bit Mode The flash memory addresses in 16-bit flash memory shift one bit down in comparison with the flash addresses in PFL II IP core. The flash address in the flash memory starts from bit 1 instead of bit 0.
  • Page 86 Follow these steps to create a single PFL II IP instantiation for programming and configuration control: 1. In the IP Catalog locate the Parallel Flash Loader II Intel FPGA IP. 2. On the General tab for What operating mode will be used, select Flash Programming and FPGA Configuration.
  • Page 87 2. On the General tab for What operating mode will be used, select Flash Programming Only. 3. Intel recommends that you turn on the Set flash bus pins to tri-state when not in use. 4. Specify the parameters on the Flash Interface Settings and Flash Programming tabs to match your design.
  • Page 88 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Example 2. Set output delay for PFL II IP output pins Example below sets the output delay for the pins. AvST_DATA AvST_VALID set avst_data_tracemax 0.250 set avst_data_tracemin 0.000 set avst_clk_tracemax 0.250 set avst_clk_tracemin 0.000 set fpga_Tsu 2.100...
  • Page 89 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 set flash_out_min_dly [expr $flash_data_tracemin - $flash_Th - $flash_clk_tracemax] set_output_delay -add_delay -max \ -clock [get_clocks {FLASH_CLK}] $flash_out_max_dly [get_ports {flash_dc1_io1 flash_dc1_io3 flash_dc1_io4 flash_dc1_io5 flash_dc1_io2}] set_output_delay -add_delay -min \ -clock [get_clocks {FLASH_CLK}] $flash_out_min_dly [get_ports { flash_dc1_io1 flash_dc1_io3 flash_dc1_io4 flash_dc1_io5 flash_dc1_io2}] Example 6.
  • Page 90 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 #Note: For normal mode, the clock is referred to input pfl_clk clock(clk_50m_max5) of PFL II IP. #If burst mode is used, the clock is referred to flash clock of PFL II IP.
  • Page 91 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Example 11. Set input delay to PFL II IP input pins Example below sets the input delay for the pin. pfl_flash_access_granted • You don't have to constraint the path when you use the device arbiter logic to control the pin, •...
  • Page 92 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins Example 15. Set output delay to PFL II IP output pins Example below sets the output delay for the output pin. pfl_flash_access_request •...
  • Page 93 .pof 1. Click File Programming File Generator. 2. For Device family select Intel Agilex. 3. For Configuration mode select Avalon-ST configuration scheme that you plan to use. 4. For Output directory, click Browse to select your output file directory. 5. For Name specify a name for your output file.
  • Page 94 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 32. Programming File Generator Output Files Tab Select Device and Configuration Mode Select Output Files To Generate, Input File Source, and Configuration Device Generate Selected Files 8. To specify a that contains the configuration bitstream, on the Input Files tab, click Add Bitstream.
  • Page 95 683673 | 2021.10.29 Figure 33. Input Files Tab Input Files 9. To include raw data, click Add Raw Data and specify a Hexadecimal (Intel-Format) Output File ( ) or binary ( .hex .bin file. This step is optional. 10. On the Configuration Device tab, click Add device. The Add Device dialog box appears. Select your flash device from the drop-down list of available parallel flash devices.
  • Page 96 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 34. Edit Partition: OPTIONS for Flash Device Start address 12. With the flash device selected, click Add Partition to specify a partition in flash memory. Intel ® Agilex ™ Configuration User Guide...
  • Page 97 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 35. Add Flash Device and Partition Configuration Device a. For Name select a Partition name. b. For Input File specify the .sof From the Page dropdown list, select the page to write this .sof...
  • Page 98 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 e. For Block and Start options, specify the address information. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 99 683673 | 2021.10.29 3.1.7.5.2. Programming CPLDs and Flash Memory Devices Sequentially This procedure provides a single set of instructions for the Intel Quartus Prime Programmer to configure the CPLD and write the flash memory device. 1. Open the Programmer and click Add File to add the for the CPLD.
  • Page 100 Add a new Intel- or AMD-compatible CFI flash memory device into the PFL II-supported flash database. Edit Edit the parameters of the newly added Intel- or AMD-compatible CFI flash memory device in the PFL II-supported flash database. Remove Remove the newly added Intel- or AMD-compatible CFI flash memory device from the PFL II-supported flash database.
  • Page 101 Specify the CFI flash extended device identifier, only applicable for AMD-compatible CFI flash memory device Flash device is Intel compatible Turn on the option if the CFI flash is Intel compatible Typical word programming time Typical word programming time value in µs unit Maximum word programming time Maximum word programming time value in µs unit...

  • Page 102: As Configuration

    3.2. AS Configuration In AS configuration schemes, the SDM block in the Intel Agilex device controls the configuration process and interfaces. The serial flash configuration device stores the configuration data. During AS Configuration, the SDM first powers on with the boot ROM.

  • Page 103: As Configuration Scheme Hardware Components And File Types

    You use the following components to implement the AS configuration scheme: • Quad SPI flash memory • The Intel FPGA Download Cable II to connect the Intel Quartus Prime Programmer to the PCB. (12) Even if not currently utilized, connect the pin to ensure future compatibility. Intel ®...
  • Page 104 When using the Micron QSPI flash memory, the boot ROM uses the AS x4 mode to load the initial configuration firmware faster to meet the PCIe wake-up time for host enumeration. When using other flash memory types for PCIe designs, the boot ROM reads the firmware using AS x1 mode. Intel recommends asserting the...
  • Page 105 SDM firmware programming. The helper SOF image provides the required SDM firmware. You initially use the JTAG cable to load a SDM Helper SOF into the Intel Agilex device. The SDM can then load the flash device with the Intel Agilex design.

  • Page 106: As Single-Device Configuration

    3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 3.2.2. AS Single-Device Configuration Figure 38. Connections for AS x4 Single-Device Configuration CCIO_SDM Configuration 10kΩ Control Signals 10kΩ Intel FPGA nCONFIG Resistor values can vary between 1 kΩ to 10 kΩ. nSTATUS...

  • Page 107: As Using Multiple Serial Flash Devices

    683673 | 2021.10.29 3.2.3. AS Using Multiple Serial Flash Devices Intel Agilex devices support one AS x4 flash memory device for AS configuration and up to three AS x4 flash memories for use with HPS data storage. The pins operate as only during POR state.

  • Page 108: As Configuration Timing Parameters

    3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 The following table shows the maximum supported frequency for a range of capacitance loading values when using AS_CLK multiple flash devices. The maximum frequency also depends on whether you use the or internal...

  • Page 109: Maximum Allowable External As_Data Pin Skew Delay Guidelines

    71.5 MHz 50 MHz 25 MHz Note: For more information about the timing parameters, refer to the Intel Agilex Device Datasheet. 3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines You must minimize the skew on the AS data pins. Intel ®...

  • Page 110: Programming Serial Flash Devices

    AS_DATA0 AS_DATA3 AS_nCSO0 AS_nCSO3 via the AS header. If you are using the Generic Serial Flash Interface Intel FPGA IP to write the flash memory the flash device must be connected to GPIO to access the flash device. Intel ®...
  • Page 111 683673 | 2021.10.29 Attention: When you power up the Intel Agilex device with an empty serial flash device and use the AS interface to program the .rpd file into this serial flash device, you must power cycle the Intel Agilex device to configure the device from the flash successfully.
  • Page 112 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 3.2.6.2. Programming Serial Flash Devices using the JTAG Interface The Intel Quartus Prime Programmer interfaces to the SDM device through JTAG interface and programs the serial flash device. Figure 43. Programming Your Serial Configuration Device Using JTAG...
  • Page 113 AS fast mode: Pull MSEL [1] low using 4.7 kΩ resistor AS normal mode: Pull MSEL [1] high using 4.7 kΩ resistor Intel recommends using the JTAG interface to prepare the Quad SPI flash device for later use in AS mode. Intel ® Agilex ™...

  • Page 114: Serial Flash Memory Layout

    AS x4 flash device using SDM_IOs. 4. If your current pins are not set to AS fast or normal mode in order to configure the Intel Agilex device in AS mode MSEL after successful programming of the flash device, set the...

  • Page 115: As_Clk

    Once loaded, if the flash size is 256 Mb or larger, the SDM configures the Quad SPI flash to operate in 4-byte addressing mode and continues to load the rest of the bitstream until configuration completes. Intel Agilex devices support the following third-party flash devices operating at 1.8 V: •...

  • Page 116: Active Serial Configuration Software Settings

    AS x4 configuration. 3.2.9. Active Serial Configuration Software Settings You must set the parameters in the Device and Pin Options of the Intel Quartus Prime software when using the AS configuration scheme. To set the parameters for AS configuration scheme, complete the following steps: 1.

  • Page 117: Intel Quartus Prime Programming Steps

    If you are generating an for remote system update (RSU), you must follow the instructions in Generating an Application .rpd Image on page 187 in the Remote System Update chapter. This procedure generates flash programming files for Intel Agilex devices. Intel ® Agilex ™...
  • Page 118 Complete the following steps to generate the programming file or files you require: 1. Click File Programming File Generator . 2. For Device Family select Intel Agilex 3. In the Configuration mode, select Active Serial x4. 4. Specify the Output directory and Name for the file you generate.
  • Page 119 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 47. Programming File Generator Input Files Input Files 8. On the Configuration Device tab, click Add Device. You can select your flash device from the Configuration Device list, or define a custom device using the available menu options. For more information about defining a custom...
  • Page 120 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 48. Programming File Generator: Configuration Device Tab Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 121 .pof .jic configuration device. The Intel Quartus Prime Programmer uses this additional data to establish communication with the configuration device and then write the programming data. 9. Click Generate to generate the programming file(s).
  • Page 122 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 3.2.10.3. Programming .jic files into Serial Flash Device To program the into the serial flash device through the JTAG interface, perform the following steps: .jic 1. In the Programmer window, click Hardware Setup and select the desired download cable.

  • Page 123: Debugging Guidelines For The As Configuration Scheme

    Intel Agilex device begins accessing the AS x4 device. When using AS fast mode, all power supplies to the Intel Agilex device must be fully ramped-up to the recommended operating conditions before the SDM releases from reset. To meet the PCIe 100 ms power-up-to-active time requirement for CvP, all the power supplies to the Intel Agilex device must be at the recommended operating range within 10 ms.

  • Page 124: Jtag Configuration

    If you are using AS x4 flash memories with AS Fast mode, you must ramp up all power supplies to the recommended operating condition within 10 ms. This ramp-up requirement ensures that the AS x4 device is within its operating voltage range when the Intel Agilex device begins to access it. •...
  • Page 125 FPGA design information. You can use .sof .rbf file with a JTAG programmer to configure the Intel Agilex device. The Intel FPGA Download Cable II and the .sof .rbf Intel FPGA Ethernet Cable both can support the V supply at 1.8 V.

  • Page 126: Jtag Configuration Scheme Hardware Components And File Types

    3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Related Information Programming Support for Jam STAPL Language 3.3.1. JTAG Configuration Scheme Hardware Components and File Types The following figure illustrates JTAG programming. This is the simplest device configuration scheme. You do not have to use...

  • Page 127: Jtag Device Configuration

    The configuration data is available on the pin one clock cycle later. You can configure the Intel Agilex device through JTAG using a download cable or a microprocessor. Intel ® Agilex ™...
  • Page 128 3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 3.3.2.1. JTAG Single-Device Configuration using Download Cable Connections Figure 51. Connection Setup for JTAG Single-Device Configuration using Download Cable CCIO_SDM 10k Ω Configuration 10kΩ Control Signals Intel FPGA nCONFIG nSTATUS Optional CONF_DONE...
  • Page 129 Intel FPGA Download Cable II User Guide • Intel Agilex Device Family Pin Connection Guidelines 3.3.2.2. JTAG Single-Device Configuration using a Microprocessor Refer to the Intel Agilex Device Family Pin Connection Guidelines for additional information about individual pin usage and requirements. Intel ®...

  • Page 130: Jtag Multi-Device Configuration

    3. Intel Agilex Configuration Schemes 683673 | 2021.10.29 Figure 52. Connection Setup for JTAG Single-Device Configuration using a Microprocessor CCIO_SDM CCIO_SDM Configuration 10kΩ Control Signals 10kΩ Intel FPGA nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE Optional OSC_CLK_1 MSEL MSEL[2:0] Resistor values can vary between 1 kΩ...
  • Page 131 For JTAG in conjunction with another configuration scheme: Resistor values can vary between 1 kΩ to 10 kΩ. Connect MSEL [2:0] of Intel FPGA devices based on the non-JTAG configuration scheme. Perform signal integrity to select the resistor value for your setup. Intel ®...

  • Page 132: Debugging Guidelines For The Jtag Configuration Scheme

    Intel Quartus Prime Pro Edition Programmer generates for error reporting. Note: For Intel Agilex SX devices when you choose to configure the FPGA fabric first, the JTAG chain has no mechanism to redeliver the HPS boot information following a cold reset. Consequently, you must reconfig the device with the file or avoid cold .sof...
  • Page 133 AS configuration mode, erase the QSPI flash device by loading MSEL file in the Intel Quartus Prime Programmer without configuring the helper image, start erasing the QSPI flash .jic device, and then power cycle the board before retrying the JTAG configuration.

  • Page 134: Including The Reset Release Intel Fpga Ip In Your Design

    FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or 9001:2015 service described herein except as expressly agreed to in writing by Intel.

  • Page 135: Understanding The Reset Release Ip Requirement

    The continual increases in clock frequency, device size, and design complexity now necessitate a reset strategy that considers the possible effects of slight differences in the release from reset. The Reset Release Intel FPGA IP holds a control circuit in reset until the device has fully entered user mode.
  • Page 136 To gate the write enable of design blocks such as embedded memory blocks, state machine, and shift registers. • To synchronously drive register reset input ports in your design. Attention: If you use multiple Reset Release Intel FPGA IP instances in your design, the signals are driven directly from the nINIT_DONE same source in SDM.

  • Page 137: Instantiating The Reset Release Ip In Your Design

    In older FPGA device families, designs frequently used the PLL lock signal to hold the custom FPGA logic in reset until the PLL locked. In newer Intel device families the lock time of PLLs can be less than the initialization time. In some cases the PLL may lock before the device completes initialization.

  • Page 138: Guidance When Using Partial Reconfiguration (Pr)

    The Reset Release IP is not necessary to prevent interaction between the static and PR personas during the PR process. For more information about PR refer to the Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration. Related Information Creating a Partial Reconfiguration Design 4.5.
  • Page 139 Release From Reset The following topics provide more detail about device configuration and initialization, and possible consequences if you do not use the Reset Release IP to hold the Intel Agilex device in reset until entire fabric enters user mode. Intel ®...

  • Page 140: Device Initialization

    6. The FPGA is now in user mode and ready for operation. 4.5.2. Preventing Register Initialization During Power-On If not held in reset, both ALM and Intel Hyperflex registers may lose their initial state if they initialize before their respective source.
  • Page 141 4. Including the Reset Release Intel FPGA IP in Your Design 683673 | 2021.10.29 Figure 58. Disabling Register Initialization During Power-On Turn On Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 142: Embedded Memory Block Initial Conditions

    4. Including the Reset Release Intel FPGA IP in Your Design 683673 | 2021.10.29 Note: Coming out of reset, you cannot rely on the value of registers with initial conditions unless you gate your system reset using one of the following options: •...
  • Page 143 4. Including the Reset Release Intel FPGA IP in Your Design 683673 | 2021.10.29 Register B in the active section is operational and takes on the value of Register A in the next clock cycle. Register A is still in the freeze register state and does not respond to the clock edge.

  • Page 144: Remote System Update (Rsu)

    FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or 9001:2015 service described herein except as expressly agreed to in writing by Intel.
  • Page 145 An Intel Agilex version of the Intel Stratix 10 SoC Remote System Update (RSU) User Guide is not yet available. The RSU SoC implementation in Intel Agilex is very similar to the implementation in Intel Stratix 10. Related Information Remote Update Intel FPGA IP User Guide Intel ®...

  • Page 146: Remote System Update Functional Description

    Firmware to identify and load the highest priority image. Previous versions of this user guide refer to decision firmware as static firmware. Starting in version 19.1 of the Intel Quartus Prime software, you can use RSU to update this firmware.
  • Page 147 • The decision firmware • The decision firmware data Intel recommends that your factory update image include the minimum amount of logic necessary to debug successfully your design if your application image or images fail to load. Intel ® Agilex ™...

  • Page 148: Remote System Update Using As Configuration

    • Designs that do not use the HPS as the remote system update host require a Mailbox Client Intel FPGA IP as shown in the figure below. The Mailbox Client sends and receives remote system update operation commands and responses, such as...

  • Page 149: Remote System Update Configuration Images

    Depending on the storage space of your flash memory, Intel Agilex remote system update supports one factory image and up to 507 application images. The Quartus Programming File Generator only supports up to seven remote system update images.

  • Page 150: Remote System Update Configuration Sequence

    Remote Update Application Application Image Application Remote Update to Application Image Images to Factory Image Image Application Image Enter User Mode Enter User Mode with Factory with Application Image Image Application Image Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 151: Rsu Recovery From Corrupted Images

    5.1.5. RSU Recovery from Corrupted Images When an RSU fails, the Mailbox Client Intel FPGA IP command provides information about the current RSU_STATUS configuration status, including the currently running image and most recent failing image. The script implements rsu1.tcl...
  • Page 152 RSU_STATUS includes the following information: — Current_Image: Application Image0 — : records information Highest priority failing image State Version Error location Error details for Application Image3 which is the highest priority failing image. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 153 Application Image2 - Corrupt Address Offset <O> * 64 KB Last Failing Image Application Image3 - Corrupt Highest Priority Address Offset <P> * 64 KB Failing Image Related Information Operation Commands on page 158 Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 154: Updates With The Factory Update Image

    If there are errors in the firmware or in the factory image Intel provides a safe solution for you to update the factory image and the associated decision firmware and decision firmware data remotely. The update process stores multiple copies of critical data so that if power is lost or the update is disrupted, the device is still able to restart and continue the update.

  • Page 155: Guidelines For Performing Remote System Update Functions For Non-Hps

    (SDM) Master Bridge) Here are guidelines to follow when implementing remote system update: 1. The factory or application image must at least contain a remote system update host controller and the Mailbox Client Intel FPGA IP. • You can use either custom logic, the Nios II processor, or the JTAG to Avalon Master Bridge IP as a remote system update host controller.

  • Page 156: Commands And Responses

    Block Diagram The following figure illustrates the role of the Mailbox Client Intel FPGA IP in a Intel Agilex design. The Mailbox Client IP enables communication with the SDM to access quad SPI flash memory and system status. Intel ®...
  • Page 157 5. Remote System Update (RSU) 683673 | 2021.10.29 Mailbox Client Role FPGA Core Fabric Host Controller Mailbox Client Intel FPGA IP JTAG FIFO Avalon-ST Avalon-MM Avalon Master Controller Interface Interface Secure Mailbox Device FIFO Nios II Driver Manager Processor Custom...

  • Page 158: Operation Commands

    5.3.1. Operation Commands Resetting Quad SPI Flash Important: For Intel Agilex devices, you must connect the serial flash or quad SPI flash reset pin to the pin. The SDM must fully AS_nRST control the QSPI reset. Do not connect the quad SPI reset pin to any external host.
  • Page 159 Upper 16 bits: Major error code. • Lower 16 bits: Minor error code. Refer to Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions in the Mailbox Client Intel FPGA IP User Guide for more information. Quartus Version Available in Intel Quartus Prime software versions between 19.4 and 21.2, the field displays:...
  • Page 160 • Bit [27:24]: Reserved • Bit [23:16]: Value is '0' Available in Intel Quartus Prime software version 21.3 or later, the Quartus version displays: • Bit [31:28]: Index of the firmware or decision firmware copy that was used the most recently.
  • Page 161 • Bit [15:0]: Minor error code Returns 0 for no failures. Refer to Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions in the Mailbox Client Intel FPGA IP User Guide for more information. Version RSU interface version and error source. For more information, refer to RSU Status and Error Codes section in the Hard Processor System Remote System Update User Guide.
  • Page 162 0x00060000: Clear error status information. • All other values are reserved. This command is not available before version 19.3 of the Intel Quartus Prime Pro Edition software. Requests exclusive access to the quad SPI. You issue this request before any other QSPI requests.
  • Page 163 Writes data to the quad SPI device. The maximum transfer size is 4 kilobytes (KB) or 1024 words. QSPI_WRITE Takes three arguments: continued... (14) This number does not include the command or response header. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 164 158. Writes to registers of the quad SPI. The maximum write is 8 bytes. Takes three arguments: QSPI_WRITE_ DEVICE_REG continued... (14) This number does not include the command or response header. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 165 158. major and minor error code descriptions, refer to Appendix: CONFIG_STATUS and CONFIG_STATUS RSU_STATUS RSU_STATUS Error Code Descriptions in the Mailbox Client Intel FPGA IP User Guide. Related Information • Mailbox Client Intel FPGA IP User Guide: Error Code Descriptions...

  • Page 166: Error Code Responses

    Indicates that the command completed unsuccessfully due to unrecoverable hardware error. HW_ERROR 80 - 8F Indicates a command specific error due to an SDM command you used. COMMAND_SPECIFIC_ERROR SDM Command Error Name Error code Description continued... Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 167: Error Code Recovery

    Resend the command from valid source such as JTAG, HPS, or core fabric. COMMAND_INVALID_ON_SOURCE Wait for the client who opened the access to quad SPI to complete its access and then closes the exclusive CLIENT_ID_NO_MATCH access to quad SPI. continued... Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 168: Quad Spi Flash Layout

    In the standard (non-RSU) case, the flash contains four firmware images and the application image. To guard against possible corruption, there are four redundant copies of the firmware. The firmware contains a pointer to the location of the application image in flash. Intel ® Agilex ™...
  • Page 169 In the RSU case, decision firmware replaces the standard firmware. The decision firmware copies have pointers to the following structures in flash: • Decision firmware data • One factory image • Two configuration pointer blocks (CPBs) Direct to Factory Direct to Factory Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 170 Decision Firmware Decision Firmware Data Factory Image Pointer Block 0 Pointer Block 1 Application Image 1 Application Image 2 Can be updated only through an update image Can be written directly Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 171 HPS. For more information, refer to Intel Agilex Hard Processor System Remote System Update User Guide. The pointer blocks contain a list of application images to try until one of them is successful. If none is successful, the SDM loads the factory image.
  • Page 172 Note: Intel Quartus Prime patches do not change the firmware version field. All patches have the same firmware version field as the base release on top of which the patches are applied to. Both U-Boot and LibRSU enable the decision firmware versions to be queried. For examples on querying the decision firmware version for both U-Boot and Linux, refer to the Remote System Update Example section.
  • Page 173 5. Remote System Update (RSU) 683673 | 2021.10.29 Sub-partition Name Contents CPB1 Pointer block 1 Application image 1 Application image 2 Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 174 Application Image 1 Can only be updated through an update image SDM does not use Can be written directly To summarize, your view of flash memory is different from SDM view in two ways: Intel ® Agilex ™ Configuration User Guide...

  • Page 175: Detailed Quad Spi Flash Layout

    If you anticipate changes to the factory or application images, you may consider reserving additional memory space. By default, the Intel Quartus Prime Programming File Generator reserves additional 256 kB of memory space for a factory image. To increase the partition size, update the End Address value in the Edit Partition dialog box window as described in the Generating the Initial RSU Image.
  • Page 176 0xFE0 Starting with Intel Quartus Prime Pro Edition software version 20.4, the SPT header contains a CRC32 checksum that is computed over the whole SPT. The value of the CRC32 checksum filed itself is assumed as zero when the checksum is computed.
  • Page 177 175. • Read only set to 1: The system protects partition against direct writes. The Intel Quartus Programming File Generator sets these flags as follows at image creation time, then they are not changed afterward: Table 49. Flags Specifying Contents and Access...
  • Page 178 32 KB or less. When configured with a coarser erase granularity (like 64 KB for example), the operation fails. All supported flash devices offer erase granularities of 4 KB, 32 KB, and 64 KB, and the default for the current HPS software is 4 KB. (15) The offset may vary in future firmware updates. Intel ® Agilex ™...
  • Page 179 The CPB header is checked prior to use to prevent accidental use if a power failure occurred. For more information, refer to the Configuration Pointer Block Layout topic. When compressing, the client compresses (erases and Intel ®...
  • Page 180 Number of sections … 0x1F08 Address of 1st section 0x1F10 Address of 2nd section 0x1F18 Address of 3rd section 0x1F20 Address of 4th section … 0x1FFC CRC32 of 0x1000 to 0x1FFB Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 181 — In Intel Quartus Prime software version 21.1 or later, a Use relative address option is the default option to generate a single application bitstream. You do not have to specify the start address since you can program the image to any available location in the QSPI flash memory.

  • Page 182: Generating Remote System Update Image Files Using The Programming File Generator

    5.5. Generating Remote System Update Image Files Using the Programming File Generator Use the Intel Quartus Prime Programming File Generator tool to generate the Intel Agilex remote system update flash programming files. 5.5.1. Generating the Initial RSU Image Follow below steps to generate the initial RSU Image.
  • Page 183 Input file drop-down list and click OK. .sof Note: You must assign Page 0 to Factory Image. Intel recommends that you let the Intel Quartus Prime software assign the Start address of the automatically by retaining the default value for Address Mode which is FACTORY_IMAGE Auto.
  • Page 184 3. On the File menu, click Programming File Generator. 4. Select Intel Agilex from the Device family drop-down list. 5. Select the configuration scheme from the Configuration mode drop-down list. The current Intel Quartus Prime only supports remote system update feature in Active Serial x4.
  • Page 185 .jic Select. Select device family and device name. Click OK. 11. Click Generate to generate the remote system update programming files. After generating the programming file, you can proceed to program the flash memory. Intel ® Agilex ™ Configuration User Guide...
  • Page 186 5. Remote System Update (RSU) 683673 | 2021.10.29 Figure 70. Generating Remote System Update Programming Files Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 187: Generating An Application Image

    .rpd 6. In Intel Quartus Prime software version 20.4 or earlier, click the Edit… button and assign the Start address for the image in flash memory. This Start address must match the starting address of the target partition in flash memory. If the address is incorrect, the image does not load successfully when you trigger an update with this image.
  • Page 188 Note: The rsu1.tcl script that Intel provides performs the bit swap operation. Consequently, if you are using this script, set Bit swap to Off. 8. On the Input Files tab, click Add Bitstream. Change the Files of type to SRAM Object File ( ).

  • Page 189: Generating A Factory Update Image

    Alternatively, you can use the Intel Quartus Prime Pro Edition Programming File Generator to generate a factory update image ( ). You can use this image to update the decision firmware, decision firmware data, and the factory image.
  • Page 190 On the File menu, click Programming File Generator. 2. Select Intel Agilex from the Device family drop-down list. 3. Select the configuration mode from the Configuration mode drop-down list. The current Intel Quartus Prime only supports the RSU feature in the Active Serial x4 configuration mode.
  • Page 191 Note: The rsu1.tcl script that Intel provides performs the bit swap operation. Consequently, if you are using this script, set Bit swap to Off. 8. On the Input Files tab, click Add Bitstream. If necessary, change the Files of type to SRAM Object File ( ).
  • Page 192 Generate 9. Select the and then click Properties. Turn On Generate RSU factory update image. Specify the Bootloader .sof file. Note: You only have to specify the Bootloader file for Intel Agilex SX devices. Intel ® Agilex ™ Configuration User Guide...
  • Page 193 683673 | 2021.10.29 Figure 75. Turn On Remote System Firmware Upgrade Turn On 10. Click Generate to generate the RSU programming files. You can now update the Intel Agilex firmware. You can save the configuration in a file for later use. .pfg Intel ®...

  • Page 194: Command Sequence To Perform Quad Spi Operations

    4. Creating a single remote system update ( ) containing the bitstreams to add an application image in user mode. .rpd 5. Adding an application image. 6. Removing an application image. Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 195: Prerequisites

    • Your design should include the Mailbox Client Intel FPGA IP that connects to a JTAG to Avalon Master Bridge as shown the Platform Designer system. The JTAG to Avalon Master Bridge acts as the remote system update host controller for your factory and application images.

  • Page 196: Creating Initial Flash Image Containing Bitstreams For Factory Image And One Application Image

    1. On the File menu, click Programming File Generator. 2. Select Intel Agilex from the Device family drop-down list. 3. Select the configuration mode from the Configuration mode drop-down list. The current Intel Quartus Prime Software only supports remote system update feature in Active Serial x4.
  • Page 197 6. On the Input Files tab, click Add Bitstream, select the factory image file and click Open. Repeat this step for the .sof application image .sof a. Bitstream_1 is the bitstream for factory image. b. Bitstream_2 is the bitstream for application image. Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 198 .sof Assign Page: 1.Keep the default settings for Address Mode. Click OK. 12. For Flash loader click Select. Select Intel Agilex from Device family list. Select AGFA014R24A3E3VR0 for the Device name. Click OK. 13. Click Generate to generate the remote system update programming files. The Programming File Generator generates the following files: Initial_RSU_Image.jic...
  • Page 199 Configuration mode: Active Serial x4 Notes: - Data checksum for this conversion is 0xC0D25FD7 - All the addresses in this file are byte addresses After generating the programming file, you can program the flash memory. Intel ® Agilex ™ Configuration User Guide...

  • Page 200: Programming Flash Memory With The Initial Remote System Update Image

    -c 1 -m jtag -o "pvi;./output_file.jic" Alternatively, you can use the Intel Quartus Prime Programmer to program the initial RSU update image by completing the following procedure: 1. open the Programmer and click Add File. Select the generated file ( ) and click Open.

  • Page 201: Reconfiguring The Device With An Application Or Factory Image

    5. Use the command to determine which bitstream image the Programmer is using as shown in the following RSU_STATUS example: a. In the Intel Quartus Prime software, select Tools System Debugging Tools System Console to launch the system console. b. In the Tcl Console pane, type to open the example of Tcl script to perform the remote system source rsu1.tcl...

  • Page 202: Adding An Application Image

    QSPI_CLOSE command. QSPI_WRITE 2. Alternatively, the script includes the function that programs a new application image into rsu1.tcl program_flash flash memory. The following command accomplishes this task: program_flash new_application_image.rpd 0x03FF0000 1024 Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 203 You can use the function verify that the new image pointer entry value is . The function QSPI_read 0xFFFFFFFF QSPI_read takes in two arguments: 1. Start address 2. Number of words to read Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 204 0x02000000 % qspi_read 0x004a8028 1 0x02000000 Host software can now reconfigure the Intel Agilex FPGA with the new application image by asserting the pin. nCONFIG Alternatively, you can power cycle the PCB. After reconfiguration, check the current image address. The expected address is .

  • Page 205: Removing An Application Image

    0x28 0x004A8028 0x02000000 (highest priority) Figure 86. Read Current CPB Values % qspi_read 0x004A0020 1 0x004B0000 % qspi_read 0x004A0028 1 0x02000000 % qspi_read 0x004A8020 1 0x004B0000 % qspi_read 0x004A8028 1 0x02000000 Intel ® Agilex ™ Configuration User Guide Send Feedback...
  • Page 206 You can now configure the device with the old application image. The old application image has the highest priority if you power cycle the device or the host asserts the pin. You can run the report to check the status of nCONFIG rsu_status the current image address. Intel ® Agilex ™ Configuration User Guide Send Feedback...

  • Page 207: Intel Agilex Configuration Features

    FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or 9001:2015 service described herein except as expressly agreed to in writing by Intel.
  • Page 208 6. Intel Agilex Configuration Features 683673 | 2021.10.29 Figure 89. Intel Agilex CvP Configuration Block Diagram Intel FPGA CVP_CONFDONE (optional) CCIO_SDM Configuration 10kΩ 10kΩ Control Signals nCONFIG nSTATUS Optional CONF_DONE Monitoring INIT_DONE OSC_CLK_1 MSEL MSEL[2:0] Configuration Control Signals FPGA Fabric...

  • Page 209: Partial Reconfiguration

    This methodology is effective in systems with multiple functions that time-share the same FPGA device resources. PR enables the implementation of more complex FPGA systems. Related Information Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration Intel ®...

  • Page 210: Intel Agilex Debugging Guide

    FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or 9001:2015 service described herein except as expressly agreed to in writing by Intel.
  • Page 211 25, 100, or 125 MHz? OSC_CLK_1 For Intel Agilex SX parts ensure that the HPS and EMIF IOPLL reference clocks are stable and free running before configuration begins. The actual frequency should match the setting specified in Platform Designer.

  • Page 212: Intel Agilex Configuration Architecture Overview

    This configuration architecture is different from earlier Intel FPGA device families where state machines control configuration. There are important differences between Intel Agilex and Intel Stratix 10 devices and previous device families with respect to available configuration modes, configuration pin behavior, and connection guidelines. In addition, the bitstream format is different.

  • Page 213: Configuration File Format Differences

    The firmware section is not part of the file. The Intel Quartus Prime Pro Edition Programmer adds the firmware to .sof . The programmer adds the firmware when configuring an Intel Agilex device or when it converts the .sof .sof another format.

  • Page 214: Understanding Seus

    7.6. Reading the Unique 64-Bit CHIP ID The Chip ID Intel FPGA IP in each Intel Agilex device stores a unique 64-bit chip ID. Refer to the Mailbox Avalon ST Client IP User Guide learn how to read the Chip ID from the Intel Agilex device.

  • Page 215: Understanding And Troubleshooting Configuration Pin Behavior

    7. Intel Agilex Debugging Guide 683673 | 2021.10.29 The reference clock is necessary to generate a pseudo-random data signal to prevent the transceiver from degrading over time. You must instantiate at least one dummy channel in the E-tile using the Native PHY IP GUI. Provide this channel at least one reference clock.
  • Page 216 Internal Oscillator option in the Intel Quartus Prime. OSC_CLK_1 • Try configuring the Intel Agilex device with a simple design that does not contain any IP. If configuration via a non-JTAG scheme fails with a simple design, try JTAG configuration with the pins set specifically to JTAG.
  • Page 217 FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or 9001:2015 service described herein except as expressly agreed to in writing by Intel.
  • Page 218 FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or 9001:2015 service described herein except as expressly agreed to in writing by Intel.
  • Page 219 Revised JTAG Configuration • Removed QSF Assignment for AS topic. • Added video describing reset importance in the Including the Reset Release Intel FPGA IP in Your Design. • Revised attention note in Understanding the Reset Release IP Requirement. •...
  • Page 220 Clarified usage of Use relative address option in the Application Image Layout and Generating an Application Image sections. • Added new video guide about debugging SDM-related configuration issues in Intel Agilex Debugging Guide. • Updated the following figures and diagrams: —...
  • Page 221 Changes Prime Version • Revised footnote in the Intel Agilex Configuration Scheme, Data Width, and MSEL table. CvP protocol is not available for the PCIe Gen3x8 and Gen4x8 in the P-tile device. • Revised Additional Clock Requirements for HPS and Transceivers. Removed mention of PCIe and HBM2 IP.
  • Page 222 Updated Programming Serial Flash Devices using the AS Interface and Debugging Guidelines for the AS Configuration Scheme with the following text: When you power up the Intel Agilex with an empty serial flash device and use the AS interface to program the .rpd file into this serial flash device, you must power cycle the Intel Agilex device to configure the device from the flash successfully.
  • Page 223 • Added note on using the Parallel Flash Loader to program multiple QSPI flash devices in the IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core: Functional Description section. • Corrected I/O voltage standard in the Debugging Guidelines for the Avalon-ST Configuration Scheme section. The I/O Bank 3A supports 1.2 V, not 1.8V.
  • Page 224 • Removed outdated text from the Understanding the Reset Release IP Requirement section. The text stated that an Intel Quartus Prime Pro Edition legality check prevents you from instantiating more than one instance of the Reset Release Intel FPGA IP.
  • Page 225 — In the JTAG Configuration section, added text: If an error occurs during JTAG configuration, the SDM does not assert signal. You can monitor the error messages that the Intel Quartus Prime Pro Edition Programmer generates nSTATUS for error reporting.
  • Page 226 Error Codes table. UNKNOWN_BR • Removed PUF data from flash memory section and figures. For more information, refer to the Intel Stratix 10 Device Security User Guide. • Revised step on selecting factory and application images in the Generating the Initial RSU Image and the Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image sections.
  • Page 227 Made the following changes: • Corrected Data Width (bits) field for CvP in Table 1. Intel Agilex Configuration Data Width, Clock Rates, and Data Rates. Intel Agilex support x8 and x16 CvP for the Gen3 and Gen4 data rates. 2019.12.16 19.4...
  • Page 228 Changed the err status pulse range from 1 ms ±50% to 0.5 ms to 10 ms. • Removed the SDM Firmware state from the Intel Intel Agilex FPGA Configuration Flow diagram. This state is part of the FPGA Configuration state.
  • Page 229 — Clarified the behavior of the pins in AS x4 mode. MSEL — Added information about the SDM_IO pin states during power-on and after device cleaning to the Intel Agilex Configuration Pins topic. — Created separate topics covering partial configuration and SmartVID signals.
  • Page 230 9. Document Revision History for the Intel Agilex Configuration User Guide 683673 | 2021.10.29 Document Version Intel Quartus Changes Prime Version • Removed vector for in the Configuration, Reconfiguration, and Error Timing Diagram figure. Power_Supply_Status • Corrected the Intel Agilex FPGA Configuration Flow diagram. The transition between...

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