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Document Version
Intel Quartus
Prime Version
2021.03.29
Intel
®
Agilex
™
Configuration User Guide
220
•
Corrected T
maximum value for
ext_delay
t
as a Function of
ext_delay
•
Revised AS_CLK topic:
— Updated
OS_CLK_1
Devices table. Added table's description.
— Added note to clarify configuration behavior for invalid
•
Corrected address in the Debugging Guidelines for the AS Configuration Scheme. The firmware load should start from
addresses 0, 512k, 1024k, and 1536k.
•
Revised the steps for image update in the Updates with the Factory Update Image section.
•
Revised Command List and Description table. Updated description for:
—
RSU_STATUS
—
QSPI_OPEN
—
QSPI_SET_CS
—
QSPI_ERASE
•
Revised RSU Image Layout in Flash - SDM Perspective. Updated
•
Revised step 2 in the Command Sequence To Perform Quad SPI Operations. The
the AS x4 configuration and mandatory for the JTAG configuration scheme.
•
Added new topic: Firmware Version Information
•
Clarified usage of Use relative address option in the Application Image Layout and Generating an Application Image
sections.
•
Added new video guide about debugging SDM-related configuration issues in Intel Agilex Debugging Guide.
•
Updated the following figures and diagrams:
— Intel Agilex Configuration Interfaces
— Power-On, Configuration, and Reconfiguration Timing Diagram
— Recoverable Error during Reconfiguration Timing Diagram
— Intel Agilex FPGA Configuration Flow
— SDM I/O pins selection in the Specifying Optional Configuration Pins section
— Configuration Pin Selection in the Intel Quartus Prime Pro Edition Software
— Dual-purpose pins selection in the Enabling Dual-Purpose Pins section
— Specifying the Slave Device Type for Power Management and VID
— Specifying the Page Command Setting
— Configuration clock source selection in the Setting Configuration Clock Source section
— AS configuration scheme setting in the Active Serial Configuration Software Settings section
•
Corrected minor errors and spelling mistakes.
21.1
Made the following changes:
9. Document Revision History for the Intel Agilex Configuration User Guide
Changes
configuration clock source at 166 MHz from 15 ns to 13.5 ns in the
OSC_CLK_1
Frequency table.
AS_CLK
description in the Supported Configuration Clock Source and
AS_CLK
683673 | 2021.10.29
Frequencies in Intel Agilex
AS_CLK
setting.
parameter value description.
max_retry
command is optional for
QSPI_SET_CS*
continued...
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