Intel Agilex Series Configuration User Manual page 208

Figure 89. Intel Agilex CvP Configuration Block Diagram
Intel ® Agilex ™ Configuration User Guide
208
V
CCIO_SDM
Configuration
10kΩ 10kΩ
Control Signals
Optional
Monitoring
AS x4 Flash Memory
DATA[3:0]
DCLK
nCS0
Periphery
Image (.jic)
PCIe Host
Root
Complex
n
3
2
Core Image 1
(.rbf)
Intel FPGA
CVP_CONFDONE (optional)
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
3
MSEL MSEL[2:0]
Configuration
Control Signals
4
AS_DATA[3:0]
AS_CLK
AS_nCSO[0]
PCIe Link
PCIe
End
Hard IP
Point
(HIP)
Core Image
Update via
PCIe Link
6. Intel Agilex Configuration Features
683673 | 2021.10.29
FPGA Fabric
Core Image
Secure
Device
Manager
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