Intel Agilex Series Configuration User Manual page 225

9. Document Revision History for the Intel Agilex Configuration User Guide
683673 | 2021.10.29
Document Version Intel Quartus
Prime Version
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• Updated Intel Agilex Configuration Timing Diagram section:
— Updated the Intel Agilex Configuration Timing Diagram figure:
• Renamed figure from Configuration, Reconfiguration, and Error Timing Diagram to Power On, Configuration, and
Reconfiguration Timing Diagram.
• Aligned Power On Reset line depicted in the figure with the Power On configuration state.
• Aligned ,
nSTATUS MSEL[2:0]
configuration state.
•
Reduced a gap between
nCONFIG
• Updated signal during Reconfiguration stage.
GPIO Status
• Removed Configuration Error portion of the timing diagram. Added separate timing diagram for the recoverable and
unrecoverable configuration error in the Configuration Error section.
— Renamed Configuration Error section to Recoverable Configuration Error. Added timing diagram. Revised
content.
— Added new section: Unrecoverable Configuration Error. Added timing diagram for unrecoverable error during the
reconfiguration.
— Revised statement on I/O pins in the POR state in the Power Supply Status section. I/O pins and programming
registers remain as don't care if POR doesn't meet the specified time.
• Updated Intel Agilex Configuration Flow Diagram:
— Revised the Intel Agilex FPGA Configuration Flow diagram.
— Revised Power Up section.
— Added text in the Configuration Start section specifying that the power management activity is ongoing during
configuration.
— In the JTAG Configuration section, added text: If an error occurs during JTAG configuration, the SDM does not assert
signal. You can monitor the error messages that the Intel Quartus Prime Pro Edition Programmer generates
nSTATUS
for error reporting.
— Added new section: Device Response to Configuration and Reset Events.
• Added clarification on E-tile variants in the Additional Clock Requirements for HPS, PCIe, eSRAM, and HBM2 section.
Replaced E-tile variants with E-tile transceiver reference clocks.
• Updated figure in the Specifying Optional Configuration Pins section.
• Updated OSC_CLK_1 Clock Input:
— Added text: When you specify
OSC_CLK_1
clock..
— Corrected frequency range in the OSC_CLK1 Input section. The frequency range is 160-230 MHz.
OSC_CLK_1
— Removed .qsf file example. Use the Intel Quartus Prime Pro Edition GUI to specify frequencies.
— Expanded topic to include additional usage requirements.
Changes
, and signals with the transition between Power On and SDM Start
AVST_READY
rising edge and rising edge to emphasize a very small time period.
nSTATUS
for configuration, the
OSC_CLK_1
nCONFIG
clock must be a stable and free-running
continued...
Intel ® Agilex ™ Configuration User Guide
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